公开(公告)号：US20220382464A1

公开(公告)日：2022-12-01

申请号：US17743137

申请日：2022-05-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sungrae KIM ,  Hyeran KIM ,  Myungkyu LEE ,  Chisung OH ,  Kijun LEE ,  Sunghye CHO ,  Sanguhn CHA

IPC: G06F3/06

Abstract: A semiconductor memory device includes a memory cell array and a cyclic redundancy check (CRC) engine. The memory cell array includes a plurality of volatile memory cells coupled to respective ones of a plurality of word-lines and respective ones of a plurality of bit-lines. The CRC engine, during a memory operation on the memory cell array, detects an error in a main data and a system parity data provided from a memory controller external to the semiconductor memory device through a link, generates an error flag indicating whether the detected error corresponds to either a first type of error associated with the link or a second type of error associated with the volatile memory cells based on the system parity data and transmit the error flag to the memory controller.

公开(公告)号：US20220139482A1

公开(公告)日：2022-05-05

申请号：US17326416

申请日：2021-05-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sungrae KIM ,  Kijun LEE ,  Myungkyu LEE ,  Hoyoun KIM ,  Suhun LIM ,  Sunghye CHO

IPC: G11C29/42 ,  G06F11/10

Abstract: A semiconductor memory device includes a memory cell array, an error correction code (ECC) engine, row fault detector circuitry and control logic circuitry. The memory cell array includes a plurality of memory cell rows. The control logic circuitry controls the ECC engine circuitry to perform a plurality of error detection operations on each of the memory cell rows. The control logic circuitry controls the row fault detector circuitry to store an error parameter associated with each of a plurality of codewords in each of which at least one error is detected by accumulating the error parameter for each of a plurality of defective memory cell rows. The row fault detector circuitry determines whether a row fault occurs in each of the plurality of defective memory cell rows based on a number of changes of the error parameter.

公开(公告)号：US20210357287A1

公开(公告)日：2021-11-18

申请号：US17132028

申请日：2020-12-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hoyoun KIM ,  Kijun LEE ,  Chanki KIM ,  Myungkyu LEE

IPC: G06F11/10 ,  H03M13/00 ,  H03M13/15

Abstract: A memory controller to control a memory module includes an error correction code (ECC) engine, a central processing unit to control the ECC engine and an error managing circuit. The ECC engine performs an ECC decoding on a read codeword set from the memory module to generate a first syndrome and a second syndrome in a read operation, corrects correctable error in a user data set based on the first syndrome and the second syndrome and provides the error management circuit with the second syndrome associated with the correctable error. The error managing circuit counts error addresses associated with correctable errors detected through read operations, stores second syndromes associated with the correctable errors by accumulating the second syndromes, determines attribute of the correctable errors based on the counting and the accumulated second syndromes, and determine an error management policy on a memory region associated with the correctable errors.

公开(公告)号：US20210193245A1

公开(公告)日：2021-06-24

申请号：US16864787

申请日：2020-05-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yesin RYU ,  Sanguhn CHA ,  Sunghye CHO ,  Kijun LEE ,  Myungkyu LEE ,  Youngcheon KWON ,  Jaeyoun YOUN

IPC: G11C29/42 ,  G11C29/44 ,  G11C29/14 ,  G11C7/10

Abstract: A semiconductor memory device includes a memory cell array and an interface circuit including an error correction code (ECC) engine. The memory cell array includes a plurality of volatile memory cells, a normal cell region and a parity cell region. The interface circuit, in a write operation, receives main data and first parity data from an external device, the first parity data being generated based on a first ECC and stores the main data in the normal cell region and the first parity data in the parity cell region. The interface circuit, in a read operation, performs an ECC decoding on the main data using a second ECC, based on the first parity data to correct a first type of error in the main data. The second ECC has a parity check matrix which is the same as a parity check matrix of the first ECC.

公开(公告)号：US20140185375A1

公开(公告)日：2014-07-03

申请号：US14196366

申请日：2014-03-04

Applicant: SAMSUNG Electronics Co., Ltd.

Inventor： Jaehong KIM ,  Kijun LEE ,  Yong June KIM ,  Heeseok EUN

IPC: G11C16/34 ,  G06F12/02

CPC classification number: G11C16/3431 ,  G06F12/0238 ,  G11C11/5642 ,  G11C16/26 ,  G11C16/3427

Abstract: Provided are a memory system and an operating method thereof. The operating method reads an observation memory cell at least one time with different read voltages to configure a first read data symbol, reads a plurality of interference memory cells adjacent to the observation memory cell at least one time with different read voltages to configure second read data symbols, and determines a logical value of the observation memory cell based on the first read data symbol and the second read data symbols.

Abstract translation: 提供了一种存储器系统及其操作方法。 操作方法用不同的读取电压至少一次读取观察存储器单元以配置第一读取数据符号，至少用不同的读取电压读取与观察存储器单元相邻的多个干扰存储器单元以配置第二读取数据 符号，并且基于第一读取数据符号和第二读取数据符号确定观察存储器单元的逻辑值。