Source side precharge and boosting improvement for reverse order program

    公开(公告)号:US11081162B1

    公开(公告)日:2021-08-03

    申请号:US16798718

    申请日:2020-02-24

    Abstract: This disclosure relates to apparatuses and a method for retaining a bias in a NAND string channel during source-side precharge. The apparatuses include a memory array and a die controller configured to mitigate formation of a potential gradient in the channel of the memory array NAND strings during a program storage operation. To this end, a plurality of source-side select gates is activated, then each of the plurality of source side dummy word line select gates is activated. Next, a NAND string channel is biased by biasing the source line coupled to the NAND string by the plurality of source-side select gates. Finally, the plurality of source-side select gates and the plurality of source side dummy word line select gates are discharged such that the channel maintains an electrical path to the source line.

    APPARATUS AND METHODS FOR SMART VERIFY WITH ADAPTIVE VOLTAGE OFFSET

    公开(公告)号:US20240203512A1

    公开(公告)日:2024-06-20

    申请号:US18355343

    申请日:2023-07-19

    CPC classification number: G11C16/3459 G11C16/10

    Abstract: An apparatus is provided that includes a control circuit coupled to a plurality of non-volatile memory cells. The control circuit is configured to perform a program-verify iteration on a first set of the non-volatile memory cells in a plurality of program loops, determine that the first set of the non-volatile memory cells passes verification to a particular programmed state in a first number of program loops, determine a first voltage based on the first number of program loops, add an adaptive voltage offset to the first voltage to obtain a second voltage, and program a second set of the non-volatile memory cells in a plurality of program loops using the second voltage. The adaptive voltage offset varies as a function of temperature.

    NON-VOLATILE MEMORY WITH OPTIMIZED OPERATION SEQUENCE

    公开(公告)号:US20240036740A1

    公开(公告)日:2024-02-01

    申请号:US17983870

    申请日:2022-11-09

    CPC classification number: G06F3/0619 G06F3/064 G06F3/0679

    Abstract: A non-volatile memory system separately performs a memory operation for multiple sub-blocks of a block in order from previously determined slowest sub-block of the block to a previously determined faster sub-block of the block. As a slower sub-block is more likely to fail, this order of is more likely to identify a failure earlier in the process thereby saving time and reducing potential for a disturb. In some embodiments, the proposed order of operation can be used in conjunction with a programming process that concurrently programs blocks in multiple planes using completion of programming of a fastest plane to a data state as a trigger to test for program failure of other planes to the data state.

    SOURCE SIDE PRECHARGE AND BOOSTING IMPROVEMENT FOR REVERSE ORDER PROGRAM

    公开(公告)号:US20210264964A1

    公开(公告)日:2021-08-26

    申请号:US16798718

    申请日:2020-02-24

    Abstract: This disclosure relates to apparatuses and a method for retaining a bias in a NAND string channel during source-side precharge. The apparatuses include a memory array and a die controller configured to mitigate formation of a potential gradient in the channel of the memory array NAND strings during a program storage operation. To this end, a plurality of source-side select gates is activated, then each of the plurality of source side dummy word line select gates is activated. Next, a NAND string channel is biased by biasing the source line coupled to the NAND string by the plurality of source-side select gates. Finally, the plurality of source-side select gates and the plurality of source side dummy word line select gates are discharged such that the channel maintains an electrical path to the source line.

    First read countermeasures in memory

    公开(公告)号:US10026486B1

    公开(公告)日:2018-07-17

    申请号:US15451186

    申请日:2017-03-06

    Abstract: Techniques are provided for improving the accuracy of read operations of memory cells, where the threshold voltage of the memory cells can shift depending on the coupled up state of the word lines. In one approach, for a read operation, a representative word line voltage in a block is detected and a corresponding set of read voltages is selected. In another approach, a pre-read voltage pulse is applied to a selected word line in response to a read command, just prior to reading the selected cells. In another approach, a voltage pulse is periodically applied to each word line in a block to provide the word lines in a coupled up state. In another approach, a soft erase is performed after a read operation to prevent coupling up of the word lines.

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