公开(公告)号：US11081162B1

公开(公告)日：2021-08-03

申请号：US16798718

申请日：2020-02-24

Applicant: SanDisk Technologies LLC

Inventor： Sarath Puthenthermadam ,  Yu-Chung Lien ,  Huai-Yuan Tseng

IPC: G11C16/04 ,  G11C11/4074 ,  G11C11/4094 ,  G11C5/14 ,  G11C7/14 ,  G11C5/02 ,  G11C11/408

Abstract: This disclosure relates to apparatuses and a method for retaining a bias in a NAND string channel during source-side precharge. The apparatuses include a memory array and a die controller configured to mitigate formation of a potential gradient in the channel of the memory array NAND strings during a program storage operation. To this end, a plurality of source-side select gates is activated, then each of the plurality of source side dummy word line select gates is activated. Next, a NAND string channel is biased by biasing the source line coupled to the NAND string by the plurality of source-side select gates. Finally, the plurality of source-side select gates and the plurality of source side dummy word line select gates are discharged such that the channel maintains an electrical path to the source line.

公开(公告)号：US10068656B2

公开(公告)日：2018-09-04

申请号：US15391006

申请日：2016-12-27

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Deepanshu Dutta ,  Sarath Puthenthermadam ,  Chris Yip

IPC: G11C16/34 ,  G11C16/10 ,  G11C16/04 ,  G11C16/26 ,  G06F3/06

CPC classification number: G11C16/3427 ,  G06F3/0619 ,  G06F3/0626 ,  G06F3/0658 ,  G06F3/0679 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/26 ,  G11C16/3459

Abstract: A non-volatile memory system implements a multi-pass programming process that includes separately programming groups of memory cells in a common block by performing programming for memory cells that are connected to two adjacent word lines and are part of a first group of memory cells followed by performing programming for other memory cells that are also connected to the two adjacent word lines and are part of a second group of memory cells.

公开(公告)号：US12249378B2

公开(公告)日：2025-03-11

申请号：US17666810

申请日：2022-02-08

Applicant: SanDisk Technologies LLC

Inventor： Yu-Chung Lien ,  Deepanshu Dutta ,  Sarath Puthenthermadam ,  Jiahui Yuan

IPC: G11C16/10 ,  G11C16/04 ,  G11C16/08 ,  G11C16/24 ,  G11C16/26 ,  G11C16/30 ,  G11C16/34

Abstract: A non-volatile semiconductor memory device, described herein, comprises a bit line, a source line, a memory string comprising a plurality of memory cells connected in series between the source line and the bit line, and control circuitry coupled to the plurality of memory cells, the source line, and the bit line. The control circuitry is configured to: determine if a program operation is a single-bit program operation or multi-bit program operation; in response to the determination, identify a voltage level to set the source line to during performance of the program operation; and perform the program operation on the memory string, the program operation including setting the source line to the voltage level.

公开(公告)号：US20240203512A1

公开(公告)日：2024-06-20

申请号：US18355343

申请日：2023-07-19

Applicant: SanDisk Technologies LLC

Inventor： Longju Liu ,  Sarath Puthenthermadam ,  Jiahui Yuan

IPC: G11C16/34 ,  G11C16/10

CPC classification number: G11C16/3459 ,  G11C16/10

Abstract: An apparatus is provided that includes a control circuit coupled to a plurality of non-volatile memory cells. The control circuit is configured to perform a program-verify iteration on a first set of the non-volatile memory cells in a plurality of program loops, determine that the first set of the non-volatile memory cells passes verification to a particular programmed state in a first number of program loops, determine a first voltage based on the first number of program loops, add an adaptive voltage offset to the first voltage to obtain a second voltage, and program a second set of the non-volatile memory cells in a plurality of program loops using the second voltage. The adaptive voltage offset varies as a function of temperature.

公开(公告)号：US20240036740A1

公开(公告)日：2024-02-01

申请号：US17983870

申请日：2022-11-09

Applicant: SanDisk Technologies LLC

Inventor： Yihang Liu ,  Xiaochen Zhu ,  Jie Liu ,  Sarath Puthenthermadam ,  Jiahui Yuan ,  Feng Gao

IPC: G06F3/06

CPC classification number: G06F3/0619 ,  G06F3/064 ,  G06F3/0679

Abstract: A non-volatile memory system separately performs a memory operation for multiple sub-blocks of a block in order from previously determined slowest sub-block of the block to a previously determined faster sub-block of the block. As a slower sub-block is more likely to fail, this order of is more likely to identify a failure earlier in the process thereby saving time and reducing potential for a disturb. In some embodiments, the proposed order of operation can be used in conjunction with a programming process that concurrently programs blocks in multiple planes using completion of programming of a fastest plane to a data state as a trigger to test for program failure of other planes to the data state.

公开(公告)号：US20230197168A1

公开(公告)日：2023-06-22

申请号：US17549457

申请日：2021-12-13

Applicant: SanDisk Technologies LLC

Inventor： Yi Song ,  Dengtao Zhao ,  Sarath Puthenthermadam ,  Jiahui Yuan

IPC: G11C16/28 ,  G11C16/10

CPC classification number: G11C16/28 ,  G11C16/10

Abstract: A system has been described that performs differential temperature compensation based on a differential between the temperature at time of programming and temperature at time of reading for a set of data. Differential temperature compensation is useful for bulk programming/reading (e.g., many pages of data) and/or programming/reading super pages of data (multiple pages residing on different memory die).

公开(公告)号：US20230186996A1

公开(公告)日：2023-06-15

申请号：US17549471

申请日：2021-12-13

Applicant: SanDisk Technologies LLC

Inventor： Yi Song ,  Dengtao Zhao ,  Sarath Puthenthermadam ,  Jiahui Yuan

IPC: G11C16/10 ,  G11C16/26 ,  G11C16/30 ,  G11C16/24 ,  G11C7/04

CPC classification number: G11C16/102 ,  G11C16/26 ,  G11C16/30 ,  G11C16/24 ,  G11C7/04

Abstract: A system has been described that performs differential temperature compensation based on a differential between the temperature at time of programming and temperature at time of reading for a set of data. Differential temperature compensation is useful for bulk programming/reading (e.g., many pages of data) and/or programming/reading super pages of data (multiple pages residing on different memory die).

公开(公告)号：US20210264964A1

公开(公告)日：2021-08-26

申请号：US16798718

申请日：2020-02-24

Applicant: SanDisk Technologies LLC

Inventor： Sarath Puthenthermadam ,  Yu-Chung Lien ,  Huai-Yuan Tseng

IPC: G11C11/4074 ,  G11C11/4094 ,  G11C11/408 ,  G11C7/14 ,  G11C5/02 ,  G11C5/14

Abstract: This disclosure relates to apparatuses and a method for retaining a bias in a NAND string channel during source-side precharge. The apparatuses include a memory array and a die controller configured to mitigate formation of a potential gradient in the channel of the memory array NAND strings during a program storage operation. To this end, a plurality of source-side select gates is activated, then each of the plurality of source side dummy word line select gates is activated. Next, a NAND string channel is biased by biasing the source line coupled to the NAND string by the plurality of source-side select gates. Finally, the plurality of source-side select gates and the plurality of source side dummy word line select gates are discharged such that the channel maintains an electrical path to the source line.

公开(公告)号：US10229744B2

公开(公告)日：2019-03-12

申请号：US15816546

申请日：2017-11-17

Applicant: SanDisk Technologies LLC

Inventor： Deepanshu Dutta ,  Idan Alrod ,  Huai-Yuan Tseng ,  Amul Desai ,  Jun Wan ,  Ken Cheah ,  Sarath Puthenthermadam

IPC: G11C16/04 ,  G11C16/34 ,  G11C16/26 ,  G11C16/16 ,  G11C8/08 ,  G11C16/08 ,  G11C29/02 ,  G11C11/56 ,  G11C29/12

Abstract: Techniques are provided for improving the accuracy of read operations of memory cells, where the threshold voltage of the memory cells can shift depending on the coupled up state of the word lines. In one approach, for a read operation, a representative word line voltage in a block is detected and a corresponding set of read voltages is selected. In another approach, a pre-read voltage pulse is applied to a selected word line in response to a read command, just prior to reading the selected cells. In another approach, a voltage pulse is periodically applied to each word line in a block to provide the word lines in a coupled up state. In another approach, a soft erase is performed after a read operation to prevent coupling up of the word lines.

公开(公告)号：US10026486B1

公开(公告)日：2018-07-17

申请号：US15451186

申请日：2017-03-06

Applicant: SanDisk Technologies LLC

Inventor： Deepanshu Dutta ,  Idan Alrod ,  Huai-Yuan Tseng ,  Amul Desai ,  Jun Wan ,  Ken Cheah ,  Sarath Puthenthermadam

IPC: G11C16/04 ,  G11C16/34 ,  G11C16/26 ,  G11C16/16

Abstract: Techniques are provided for improving the accuracy of read operations of memory cells, where the threshold voltage of the memory cells can shift depending on the coupled up state of the word lines. In one approach, for a read operation, a representative word line voltage in a block is detected and a corresponding set of read voltages is selected. In another approach, a pre-read voltage pulse is applied to a selected word line in response to a read command, just prior to reading the selected cells. In another approach, a voltage pulse is periodically applied to each word line in a block to provide the word lines in a coupled up state. In another approach, a soft erase is performed after a read operation to prevent coupling up of the word lines.