公开(公告)号：US20240005990A1

公开(公告)日：2024-01-04

申请号：US17810097

申请日：2022-06-30

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Hirofumi TOKITA ,  Tomohiro KUBO ,  Shiqian SHAO ,  Fumiaki TOYAMA

IPC: G11C16/04 ,  H01L27/11519 ,  H01L23/522 ,  H01L23/528 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11582

CPC classification number: G11C16/0483 ,  H01L27/11519 ,  H01L23/5226 ,  H01L23/5283 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11582

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers, a first three-dimensional memory array located in a first memory array region, and a second three-dimensional memory array located in a second memory array region that is laterally spaced from the first memory array region along a first horizontal direction by an inter-array region. The alternating stack is laterally bounded by two trench fill structures that are laterally spaced apart along a second horizontal direction by an inter-trench spacing. The inter-array region includes a stepped cavity having vertical steps of the alternating stack that laterally extend along different horizontal directions. Multiple rows of contact via structures may contact different electrically conductive layers in the stepped cavity. Alternatively or additionally, a top portion of the stepped cavity and a width of a bridge region of the electrically conductive layers in the inter-array region may have a variable lateral extent along the second horizontal direction.

公开(公告)号：US20220328413A1

公开(公告)日：2022-10-13

申请号：US17807804

申请日：2022-06-20

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Tomohiro KUBO ,  Michiaki SANO

IPC: H01L23/535 ,  H01L27/11556 ,  H01L27/11582

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers, memory openings located in a memory array region and vertically extending through the alternating stack, memory opening fill structures located in the memory openings, and laterally-isolated contact via assemblies located in a contact region that is located adjacent to the memory array region. Each of the laterally-isolated contact via assemblies includes a contact via structure contacting a top surface of a respective one of the electrically conductive layers and a dielectric spacer laterally surrounding the contact via structure. Each contact via structure other than a contact via structure contacting a topmost one of the electrically conductive layers extends through and is laterally surrounded by each electrically conductive layer that overlies the respective electrically conductive layer.

公开(公告)号：US20220102273A1

公开(公告)日：2022-03-31

申请号：US17039160

申请日：2020-09-30

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Tomohiro KUBO

IPC: H01L23/528 ,  H01L27/11556 ,  H01L27/11582 ,  H01L23/522 ,  H01L21/768

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located between line trenches, a first memory array region and a second memory array region, and a pair of dielectric wall structures located between the first line trench and the second line trench and between the memory array regions. Each layer within the alternating stack continuously extends between the first memory array region and the second memory array region in a connection region. The electrically conductive layers of the alternating stack have lateral extents that decrease with a distance from the substrate in a staircase region. Dielectric material plates interlaced with insulating plates or insulating layers are provided between the dielectric wall structures.

公开(公告)号：US20250014990A1

公开(公告)日：2025-01-09

申请号：US18800545

申请日：2024-08-12

Applicant: Sandisk Technologies LLC

Inventor： Tomohiro KUBO ,  Koichi MATSUNO

IPC: H01L23/522 ,  H01L23/532 ,  H10B43/10 ,  H10B43/27

Abstract: A memory device includes an alternating stack of insulating layers and electrically conductive layers, a memory opening vertically extending through each layer within the alternating stack, a memory opening fill structure located in the memory opening and including a vertical stack of memory elements a vertical semiconductor channel, and a contact via structure. The contact via structure includes a conductive pillar portion vertically extending at least from a first horizontal plane including a bottommost surface of the alternating stack to a second horizontal plane including a topmost surface of the alternating stack, and an annular conductive fin portion laterally protruding from the conductive pillar portion and contacting one of the electrically conductive layers. A vertical stack of annular insulating plates laterally surrounds the conductive pillar portion and underlies the conductive fin portion.

公开(公告)号：US20240179904A1

公开(公告)日：2024-05-30

申请号：US18240560

申请日：2023-08-31

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Tomohiro KUBO ,  Takayuki MAEKURA

IPC: H10B43/27 ,  G11C16/04 ,  H01L23/522 ,  H01L23/528 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/35

CPC classification number: H10B43/27 ,  G11C16/0483 ,  H01L23/5226 ,  H01L23/5283 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/35

Abstract: A method includes forming an in-process alternating stack of insulating layers and sacrificial material layers, forming a meandering dielectric isolation structure through the in-process alternating stack, forming memory stack structures through the alternating stack, where each of the memory stack structures includes a respective vertical stack of memory elements and a vertical semiconductor channel, forming sacrificial via fill structures on the respective sacrificial material layers, replacing first portions of the sacrificial material layers with electrically conductive layers, and forming layer contact via structures contacting a respective one of the electrically conductive layers by replacing at least the sacrificial via fill structures with a conductive material portion.