公开(公告)号：US20230275026A1

公开(公告)日：2023-08-31

申请号：US17682515

申请日：2022-02-28

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Koichi MATSUNO ,  Kota FUNAYAMA

IPC: H01L23/535 ,  H01L23/528 ,  H01L27/11556 ,  H01L27/11582

CPC classification number: H01L23/535 ,  H01L23/5283 ,  H01L27/11556 ,  H01L27/11582

Abstract: Contact via openings are formed through a retro-stepped dielectric material portion in a three-dimensional memory device to underlying etch stop structures. The etch stop structures may include a stepped conductive or semiconductor etch stop plate overlying stepped surfaces in the staircase region. The contact via openings are extended through the etch stop structures. Alternatively, electrically conductive layers, including a topmost dummy electrically conductive layer in the staircase region, may be employed as etch stop structures. In this case, the contact via openings can be extended through the electrically conductive layers. Insulating spacers are formed at peripheral regions of the extended contact via openings. Contact via structures surrounded by the insulating spacers are formed in the extended contact via openings to a respective underlying electrically conductive layer.

公开(公告)号：US20220367499A1

公开(公告)日：2022-11-17

申请号：US17317578

申请日：2021-05-11

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Koichi MATSUNO ,  Masaaki HIGASHITANI ,  Johann ALSMEIER

IPC: H01L27/11556 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11582

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, an array of memory opening fill structures located within an array of memory openings vertically extending through the alternating stack, and a drain-select-level isolation structure vertically extending through drain-select-level electrically conductive layers between two rows of memory opening fill structures. The drain-select-level isolation structure may comprise a low-k dielectric material or an air gap.

公开(公告)号：US20220352196A1

公开(公告)日：2022-11-03

申请号：US17244258

申请日：2021-04-29

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Kenichi SHIMOMURA ,  Koichi MATSUNO ,  Johann ALSMEIER

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L27/11519 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11524

Abstract: Two types of support pillar structures are formed in a staircase region of an alternating stack of insulating layers and sacrificial material layers. First-type support pillar structures are formed in areas distal from backside trenches to be subsequently formed, and second-type support pillar structures may be formed in areas proximal to the backside trenches. The second-type support pillar structures may be formed as dielectric support pillar structures, or may be formed with at least one additional dielectric spacer.

公开(公告)号：US20210210503A1

公开(公告)日：2021-07-08

申请号：US17106792

申请日：2020-11-30

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Koichi MATSUNO ,  James KAI ,  Jixin YU ,  Johann ALSMEIER ,  Yoshitaka OTSU

IPC: H01L27/11575 ,  H01L23/522 ,  H01L27/11556 ,  H01L27/11548 ,  H01L27/11582 ,  H01L21/768

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers, memory stack structures vertically extending through the alternating stack, wherein each of the memory stack structures comprises a vertical semiconductor channel and a vertical stack of memory elements, a dielectric moat structure vertically extending through the alternating stack and including an annular dielectric plate portion at each level of the electrically conductive layers that laterally surrounds a respective dielectric material plate, and an interconnection via structure laterally surrounded by the dielectric moat structure and vertically extending through each insulating layer within the alternating stack. Each of the annular dielectric plate portions includes a continuous inner sidewall including a plurality of laterally-convex and vertically-planar inner sidewall segments that are adjoined to each other, and a continuous outer sidewall including a plurality of laterally-convex and vertically-planar outer sidewall segments that are adjoined to each other.

公开(公告)号：US20250014990A1

公开(公告)日：2025-01-09

申请号：US18800545

申请日：2024-08-12

Applicant: Sandisk Technologies LLC

Inventor： Tomohiro KUBO ,  Koichi MATSUNO

IPC: H01L23/522 ,  H01L23/532 ,  H10B43/10 ,  H10B43/27

Abstract: A memory device includes an alternating stack of insulating layers and electrically conductive layers, a memory opening vertically extending through each layer within the alternating stack, a memory opening fill structure located in the memory opening and including a vertical stack of memory elements a vertical semiconductor channel, and a contact via structure. The contact via structure includes a conductive pillar portion vertically extending at least from a first horizontal plane including a bottommost surface of the alternating stack to a second horizontal plane including a topmost surface of the alternating stack, and an annular conductive fin portion laterally protruding from the conductive pillar portion and contacting one of the electrically conductive layers. A vertical stack of annular insulating plates laterally surrounds the conductive pillar portion and underlies the conductive fin portion.

公开(公告)号：US20240334695A1

公开(公告)日：2024-10-03

申请号：US18360541

申请日：2023-07-27

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Jixin YU ,  Koichi MATSUNO ,  Ruogu Matthew ZHU ,  Johann ALSMEIER

IPC: H10B43/27 ,  H10B41/27

CPC classification number: H10B43/27 ,  H10B41/27

Abstract: A three-dimensional memory device includes laterally spaced apart vertical stacks of electrically conductive layers and insulating layers. A composite dielectric isolation structure provides electrical isolation between neighboring pairs of vertical stacks. The composite dielectric isolation structure includes at least one retro-stepped dielectric material portion, and may further include at least one finned insulating support structure or a vertical stack of dielectric material plates.

公开(公告)号：US20240250023A1

公开(公告)日：2024-07-25

申请号：US18358702

申请日：2023-07-25

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Ruogu Matthew ZHU ,  Koichi MATSUNO ,  Seyyed Ehsan Esfahani RASHIDI ,  Jixin YU ,  Johann ALSMEIER

IPC: H01L23/528 ,  G11C5/06 ,  G11C16/04 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

CPC classification number: H01L23/5283 ,  G11C5/063 ,  G11C16/0483 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H01L23/5226

Abstract: A memory device includes at least one alternating stack of respective insulating layers and respective electrically conductive layers and memory stack structures vertically extending through the at least one alternating stack. A layer contact via structure contacts a top surface of one of the electrically conductive layers, and is laterally surrounded by at least one dielectric spacer, which may include a plurality of dielectric spacers, and optionally by a plurality of dielectric support pillar structures. Additionally or alternatively, the layer contact via structure may comprise a convex surface segment that is adjoined to a straight sidewall segment.

公开(公告)号：US20240172431A1

公开(公告)日：2024-05-23

申请号：US18425996

申请日：2024-01-29

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： James KAI ,  Johann ALSMEIER ,  Lito De La RAMA ,  Masaaki HIGASHITANI ,  Koichi MATSUNO ,  Marika GUNJI-YONEOKA ,  Makoto KOTO ,  Hisakazu OTOI ,  Masanori TSUTSUMI

IPC: H10B41/27 ,  G11C7/18 ,  G11C8/14 ,  H01L29/06 ,  H10B41/10 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

CPC classification number: H10B41/27 ,  G11C7/18 ,  G11C8/14 ,  H01L29/0653 ,  H10B41/10 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a plurality of source layers, where the electrically conductive layers include word lines and source-side select gate electrodes which are located between the plurality of source layers and the word lines in a vertical direction, groups of memory openings vertically extending through the alternating stack, and groups of memory opening fill structures located in the groups of memory openings. The plurality of source layers are laterally spaced apart and electrically isolated from each other, and each respective one of the plurality of source layers contacts at least one respective group of the groups of memory opening fill structures.

公开(公告)号：US20220367487A1

公开(公告)日：2022-11-17

申请号：US17317479

申请日：2021-05-11

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Peng ZHANG ,  Yanli ZHANG ,  Xiang YANG ,  Koichi MATSUNO ,  Masaaki HIGASHITANI ,  Johann ALSMEIER

IPC: H01L27/1159 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582 ,  H01L27/11597 ,  H01L29/06 ,  H01L21/764

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, an array of memory opening fill structures located within an array of memory openings vertically extending through the alternating stack, and a drain-select-level isolation structure vertically extending through drain-select-level electrically conductive layers between two rows of memory opening fill structures. The drain-select-level isolation structure may comprise a low-k dielectric material or an air gap.

公开(公告)号：US20240276725A1

公开(公告)日：2024-08-15

申请号：US18616682

申请日：2024-03-26

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Adarsh RAJASHEKHAR ,  Senaka KANAKAMEDALA ,  Koichi MATSUNO

IPC: H10B43/27

CPC classification number: H10B43/27

Abstract: A memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, memory openings vertically extending through the alternating stack, memory opening fill structures located in the memory openings, each including a respective vertical semiconductor channel and a vertical stack of memory elements, a contact via structure contacting a reference electrically conductive layer that is one of the electrically conductive layers, and at least one silicon oxide liner laterally surrounding a cylindrical portion of the contact via structure and contacting a laterally protruding portion of the contact via structure.