公开(公告)号：US20210384193A1

公开(公告)日：2021-12-09

申请号：US17289357

申请日：2019-10-28

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Hajime KIMURA ,  Yoshiyuki KUROKAWA

IPC: H01L27/108 ,  G06N3/063

Abstract: A semiconductor device that can perform product-sum operation with low power consumption is provided. The semiconductor device includes first and second circuits. The first circuit includes a first holding node and the second circuit includes a second holding node. The first circuit is electrically connected to first and second input wirings and first and second wirings, the second circuit is electrically connected to the first and second input wirings and the first and second wirings, and the first and second circuits have a function of holding first and second potentials corresponding to first data at the first and second holding nodes. When potentials corresponding to second data are input to the first and second input wirings, the first circuit outputs a current to one of the first wiring and the second wiring, and the second circuit outputs a current to the other of the first wiring and the second wiring. The currents output by the first and second circuits to the first wiring and the second wiring are determined in accordance with the first and second potentials held at the first and second nodes.

公开(公告)号：US20210358530A1

公开(公告)日：2021-11-18

申请号：US17382692

申请日：2021-07-22

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yoshiyuki KUROKAWA ,  Shunpei YAMAZAKI

IPC: G11C11/16 ,  G06F9/4401 ,  G06F21/57 ,  G11C5/14 ,  G11C11/402 ,  G11C11/404 ,  H01L27/108

Abstract: The operation speed of a semiconductor device is improved.
The semiconductor device includes a first memory region and a second memory region; in the semiconductor device, a first memory cell in the first memory region is superior to a second memory cell in the second memory region in data retention characteristics such as a large storage capacitance or a large channel length-channel width ratio (L/W) of a transistor. When the semiconductor device is used as a cache memory or a main memory device of a processor, the first memory region mainly stores a start-up routine and is not used as a work region for arithmetic operation, and the second memory region is used as a work region for arithmetic operation. The first memory region becomes an accessible region when the processor is booted, and the first memory region becomes an inaccessible region when the processor is in normal operation.

公开(公告)号：US20210280611A1

公开(公告)日：2021-09-09

申请号：US17322954

申请日：2021-05-18

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Kei TAKAHASHI ,  Yoshiyuki KUROKAWA

IPC: H01L27/12 ,  G02F1/1362 ,  G02F1/1368 ,  H01L29/24 ,  H01L29/786

Abstract: A display device that is suitable for increasing its size is provided.
The display device includes first to third wirings, a first transistor, first to third conductive layers, and a first pixel electrode; the first wiring extends in a first direction and intersects with the second and the third wirings; the second and the third wirings each extend in a second direction intersecting with the first direction; a gate of the first transistor is electrically connected to the first wiring; one of a source and a drain of the first transistor is electrically connected to the second wiring through the first to the third conductive layers; the second conductive layer includes a region overlapping with the third wiring; the first conductive layer, the third conductive layer, and the first pixel electrode contain the same material; the first wiring and the second conductive layer contain the same material; the first wiring is supplied with a selection signal; and the second and the third wirings are supplied with different signals.

公开(公告)号：US20210257016A1

公开(公告)日：2021-08-19

申请号：US16973223

申请日：2019-05-31

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Hajime KIMURA ,  Yoshiyuki KUROKAWA ,  Tatsunori INOUE

IPC: G11C11/405 ,  G11C11/54 ,  G11C5/06 ,  G06N3/063

Abstract: In a semiconductor device capable of product-sum operation, variations in transistor characteristics are reduced. The semiconductor device includes a first circuit including a driver unit, a correction unit, and a holding unit, and an inverter circuit. The first circuit has a function of generating an inverted signal of a signal input to an input terminal of the first circuit and outputting the inverted signal to an output terminal of the first circuit. The driver unit includes a p-channel first transistor and an n-channel second transistor having a back gate. The correction unit has a function of correcting the threshold voltage of one or both of the first transistor and the second transistor. The holding unit has a function of holding the potential of the back gate of the second transistor. The output terminal of the first circuit is electrically connected to an input terminal of the inverter circuit. The time from the input of a signal to the input terminal of the first circuit to the output of a signal from an output terminal of the inverter circuit depends on the potential of the back gate of the second transistor.

公开(公告)号：US20210134801A1

公开(公告)日：2021-05-06

申请号：US16638799

申请日：2018-08-27

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Shintaro HARADA ,  Tatsunori INOUE ,  Yoshiyuki KUROKAWA ,  Shunpei YAMAZAKI

IPC: H01L27/105 ,  H01L27/12 ,  H01L29/786 ,  G06N3/063

Abstract: An electronic device including a semiconductor device capable of intermittent driving is provided. The electronic device includes a semiconductor device, and the semiconductor device includes a current mirror circuit, a bias circuit, and first to third transistors. The current mirror circuit includes a first output terminal and a second output terminal, and the current mirror circuit is electrically connected to a power supply line through the first transistor. The current mirror circuit has a function of outputting current corresponding to a potential of the first output terminal from the first output terminal and the second output terminal. The bias circuit includes a current source circuit and a current sink circuit, the current source circuit is electrically connected to the second output terminal through the second transistor, and the current sink circuit is electrically connected to the second output terminal through the third transistor. Switching on/off states of the first to third transistors achieves intermittent driving of the semiconductor device.

公开(公告)号：US20200349423A1

公开(公告)日：2020-11-05

申请号：US16934110

申请日：2020-07-21

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Yoshiyuki KUROKAWA

IPC: G06N3/063 ,  G11C7/10 ,  G11C5/06 ,  G11C7/16 ,  H01L27/12 ,  G06N3/08 ,  G11C5/14 ,  H01L29/786

Abstract: To provide a semiconductor device which can execute the product-sum operation. The semiconductor device includes a first memory cell, a second memory cell, and an offset circuit. First analog data is stored in the first memory cell, and reference analog data is stored in the second memory cell. The first memory cell and the second memory cell supply a first current and a second current, respectively, when a reference potential is applied as a selection signal. The offset circuit has a function of supplying a third current corresponding to a differential current between the first current and the second current. In the semiconductor device, the first memory and the second memory supply a fourth current and a fifth current, respectively, when a potential corresponding to second analog data is applied as a selection signal. By subtracting the third current from a differential current between the fourth current and the fifth current, a current that depends on the sum of products of the first analog data and the second analog data is obtained.

公开(公告)号：US20200320924A1

公开(公告)日：2020-10-08

申请号：US16868696

申请日：2020-05-07

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yoshiyuki KUROKAWA

IPC: G09G3/20 ,  H01L27/12 ,  H01L29/786 ,  G02F1/1335 ,  G06F1/3218 ,  G06F1/3234

Abstract: An object is to provide a semiconductor device with low power consumption. The semiconductor device includes a controller, a register, and an image processing portion. The image processing portion has a function of taking image data from a frame memory and a parameter from the register and processing the image data by using the parameter. The frame memory has a function of retaining the image data while power supply is stopped. The register has a function of retaining the parameter while power supply is stopped. The controller controls power supply to the register, the frame memory, and the image processing portion. The register includes first and second scan chain registers. The first scan chain register stores a parameter related to a first display region. The second scan chain register stores a parameter related to a second display region. A parameter is changed by loading of data of the first or second scan chain register.

公开(公告)号：US20200183483A1

公开(公告)日：2020-06-11

申请号：US16789480

申请日：2020-02-13

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Yuki OKAMOTO ,  Yoshiyuki KUROKAWA

IPC: G06F1/3234 ,  G11C11/412 ,  G06F1/3228 ,  H03K19/0175 ,  G11C11/40 ,  G06F13/42 ,  G06F1/3296 ,  G06F1/3293 ,  G06F1/3287

Abstract: A method for controlling power supply in a semiconductor device including a CPU and a PLD which can hold data even in an off state is provided. The semiconductor device includes a processor, a programmable logic device, and a state control circuit. The programmable logic device includes a first nonvolatile memory circuit and has a function of holding data obtained by arithmetic processing of the programmable logic device when it is turned off. The state control circuit obtains data on the amount of a task performed by the programmable logic device in accordance with an operation of the processor. The programmable logic device detects the state of progress of the task and outputs a signal to the state control circuit. The state control circuit monitors the amount of the task and the state of progress of the task and turns off the programmable logic device when the task is completed.

公开(公告)号：US20200176493A1

公开(公告)日：2020-06-04

申请号：US16615156

申请日：2018-05-06

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Takayuki IKEDA ,  Yoshiyuki KUROKAWA ,  Shintaro HARADA ,  Hidetomo KOBAYASHI ,  Roh YAMAMOTO ,  Kiyotaka KIMURA ,  Takashi NAKAGAWA ,  Yusuke NEGORO

IPC: H01L27/146 ,  H04N5/341 ,  H04N5/374 ,  H01L29/786 ,  H04N5/3745 ,  H01L27/12

Abstract: An imaging device capable of image processing is provided.The imaging device can retain analog data (image data) obtained by an image-capturing operation in a pixel and perform a product-sum operation of the analog data and a predetermined weight coefficient in the pixel to convert the data into binary data. When the binary data is taken in a neural network or the like, processing such as image recognition can be performed. Since enormous volumes of image data can be retained in pixels in the state of analog data, processing can be performed efficiently.

公开(公告)号：US20200099881A1

公开(公告)日：2020-03-26

申请号：US16693483

申请日：2019-11-25

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yoshiyuki KUROKAWA

IPC: H04N5/3745 ,  H01L27/146 ,  G01S17/89 ,  G01S7/481 ,  G01S7/486 ,  G01S17/02

Abstract: A driving method of a semiconductor device that takes three-dimensional images with short duration is provided. In a first step, a light source starts to emit light, and first potential corresponding to the total amount of light received by a first photoelectric conversion element and a second photoelectric conversion element is written to a first charge accumulation region. In a second step, the light source stops emitting light and second potential corresponding to the total amount of light received by the first photoelectric conversion element and the second photoelectric conversion element is written to a second charge accumulation region. In a third step, first data corresponding to the potential written to the first charge accumulation region is read. In a fourth step, second data corresponding to the potential written to the second charge accumulation region is read.