Abstract:
A motor control apparatus to control a motor external to the motor control apparatus includes a microcontroller unit (MCU). The MCU includes mixed signal motor control circuitry adapted to perform back electromotive force (EMF) motor control in a first mode of operation. The mixed signal motor control circuitry is further adapted to perform field oriented control (FOC) in a second mode of operation.
Abstract:
An apparatus includes an integrated circuit (IC) adapted to be powered by a positive supply voltage. The IC includes a charge pump that is adapted to convert the positive supply voltage of the IC to a negative bias voltage. The IC further includes a bidirectional interface circuit. The bidirectional interface circuit includes an amplifier coupled to the negative bias voltage to accommodate a bidirectional input voltage of the IC. The bidirectional interface circuit further includes a comparator coupled to the negative bias voltage to accommodate the bidirectional input voltage of the IC.
Abstract:
An integrated circuit (IC) includes a plurality of pads adapted to communicate signals with a circuit external to the IC, and a first mixed signal interface block coupled to a first pad in the plurality of pads, where the first mixed signal interface block is adapted to receive a first trigger signal from the circuit external to the IC and to provide a second trigger signal. The IC further includes a second mixed signal interface block coupled to a second pad in the plurality of pads, where the second mixed signal interface block is adapted to receive and track a first input signal from the circuit external to the IC in a first mode of operation of the IC. The second mixed signal interface block is further adapted to generate, in response to the second trigger signal, a first output signal based on the first input signal and to provide the first output signal to a digital core of the IC in a second mode of operation of the IC, where the power consumption of the IC is lower in the first mode of operation than in the second mode of operation.
Abstract:
An apparatus includes a digital battery charger. The digital battery charger includes an analog-to-digital converter (ADC) to convert a terminal voltage of a battery to a first digital signal. The digital battery charger further includes a digital controller coupled to the ADC to receive the first digital signal and provide a set of control signals. The digital battery charger further includes a current digital-to-analog converter (IDAC) coupled to the digital controller to receive the set of control signals and to provide a battery charging current signal.
Abstract:
In one embodiment, an apparatus includes a controller to control a voltage regulator. The controller may have a first comparator circuit to compare a first reference voltage to a feedback voltage. In turn, the first comparator circuit may include: a first comparator having a first input terminal to receive the feedback voltage and a second input terminal to receive the reference voltage and an output node to output an error signal based on the comparison; and a first pre-charge circuit coupled between the first input terminal and the output node configured to pre-charge a first portion of a compensation network to a pre-charge level. The first controller may further include a second comparator circuit coupled to the first comparator circuit compare the error signal to a ramp signal and to generate a first control output to control a power train of the voltage regulator in a first mode of operation.
Abstract:
Apparatus and associated methods are disclosed for gain and offset trimming. In one exemplary embodiment, an apparatus includes a first circuit that includes a first transconductance stage to generate a first current. The first circuit has an output offset. The apparatus further includes an offset trim circuit, which includes a second circuit to provide an output voltage selectable from a plurality of voltage values, and a second transconductance stage to generate a second current in response to the output voltage of the second circuit. The output offset of the first circuit is trimmed by adding the second current to the first current.
Abstract:
Apparatus and associated methods are disclosed for gain programming or selection with parasitic element compensation. In one exemplary embodiment, an apparatus includes a first circuit that has a first programmable gain, and includes a first set of components having parasitic elements. The apparatus also includes a second circuit that has a second programmable gain, and includes a second set of components having parasitic elements. The apparatus has a gain that is a product of the first and second programmable gains. A gain error because of the parasitic elements of the first and second sets of components is canceled by setting the first programmable gain as a reciprocal of the second programmable gain.
Abstract:
Apparatus and associated methods are disclosed for gain and offset trimming. In one exemplary embodiment, an apparatus includes a first circuit that includes a first transconductance stage to generate a first current. The first circuit has an output offset. The apparatus further includes an offset trim circuit, which includes a second circuit to provide an output voltage selectable from a plurality of voltage values, and a second transconductance stage to generate a second current in response to the output voltage of the second circuit. The output offset of the first circuit is trimmed by adding the second current to the first current.
Abstract:
An apparatus includes an integrated circuit (IC) adapted to be powered by a positive supply voltage. The IC includes a charge pump that is adapted to convert the positive supply voltage of the IC to a negative bias voltage. The IC further includes a bidirectional interface circuit. The bidirectional interface circuit includes an amplifier coupled to the negative bias voltage to accommodate a bidirectional input voltage of the IC. The bidirectional interface circuit further includes a comparator coupled to the negative bias voltage to accommodate the bidirectional input voltage of the IC.
Abstract:
A method includes generating one of a first clock signal and a second clock signal from the other clock signal. The first clock signal is configured to be used to synchronize an operation of an analog system, and the second clock signal is configured to be used to synchronize an operation of a digital system. The method includes using a phase detector of the analog system to measure a timing of the first clock signal relative to the second clock signal; and the method includes controlling a delay element of the digital system to regulate the timing based on the measurement by the phase detector to suppress noise in the analog system.