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    BUFFER, SEMICONDUCTOR APPARATUS AND SEMICONDUCTOR SYSTEM USING THE SAME
    11.
    发明申请
    BUFFER, SEMICONDUCTOR APPARATUS AND SEMICONDUCTOR SYSTEM USING THE SAME 审中-公开
    缓冲器，半导体器件和使用其的半导体系统

    公开(公告)号：US20170031653A1

    公开(公告)日：2017-02-02

    申请号：US14940309

    申请日：2015-11-13

    Applicant: SK hynix Inc.

    Inventor： Jin Ha HWANG ,  Dae Han KWON

    IPC: G06F5/14 ,  G11C8/18 ,  G11C7/22

    CPC classification number: G06F5/14 ,  G06F2205/126 ,  G11C5/025 ,  G11C7/02 ,  G11C7/1093 ,  G11C7/22 ,  G11C29/4401 ,  G11C29/76

    Abstract: A buffer may include a first sensing unit configured to sense data, and a second sensing unit configured to generate equalization control signals according to outputs of the first sensing unit. The buffer may include an equalization delay compensation unit configured to compensate the equalization control signals for signal processing delay times of the equalization control signals, and generate delay-compensated equalization control signals. The buffer may include a noise removal unit configured to primarily remove noise of the output signals of the first sensing unit according to the equalization control signals, and secondarily remove noise of the output signals of the first sensing unit according to the delay-compensated equalization control signals.

    Abstract translation: 缓冲器可以包括被配置为感测数据的第一感测单元和被配置为根据第一感测单元的输出产生均衡控制信号的第二感测单元。 缓冲器可以包括均衡延迟补偿单元，其被配置为补偿均衡控制信号用于均衡控制信号的信号处理延迟时间，并且生成延迟补偿的均衡控制信号。 缓冲器可以包括噪声去除单元，其被配置为根据均衡控制信号主要消除第一感测单元的输出信号的噪声，并且二次根据延迟补偿均衡控制去除第一感测单元的输出信号的噪声 信号。

    BUFFER CIRCUIT CAPABLE OF REDUCING NOISE
    12.
    发明申请
    BUFFER CIRCUIT CAPABLE OF REDUCING NOISE 有权

    公开(公告)号：US20220416790A1

    公开(公告)日：2022-12-29

    申请号：US17514789

    申请日：2021-10-29

    Applicant: SK hynix Inc.

    Inventor： Jin Ha HWANG ,  Soon Sung AN ,  Junseo JANG ,  Jaehyeong HONG

    IPC: H03K19/0185 ,  H03K19/003

    Abstract: A buffer circuit includes a power control circuit, an inverting circuit, and a voltage adjustment circuit. The power control circuit is configured to provide voltages based on an input signal and a mode signal, and the inverting circuit is configured to receive and invert the voltages to generate an output signal. The voltage adjustment circuit is configured to adjust voltage levels based on the mode signal and the output signal.

    DATA BUFFER AND MEMORY DEVICE HAVING THE SAME
    16.
    发明申请
    DATA BUFFER AND MEMORY DEVICE HAVING THE SAME 审中-公开

    公开(公告)号：US20190272857A1

    公开(公告)日：2019-09-05

    申请号：US16161272

    申请日：2018-10-16

    Applicant: SK hynix Inc.

    Inventor： Jin Ha HWANG

    IPC: G11C7/10 ,  G11C7/06 ,  G11C16/26

    Abstract: There are provided a data buffer and a memory system having the same. The data buffer includes first and second amplifiers configured to output data by inverting input data, the first and second amplifiers having coupled output nodes to which the output data is output, wherein both of the first and second amplifiers are activated to output the output data when the input data has a first swing level, and wherein one of the first and second amplifiers is activated to output the output data when the input data has a second swing level narrower than the first swing level.

    SIGNAL RECEIVING DEVICE, AND A SEMICONDUCTOR APPARATUS AND A SEMICONDUCTOR SYSTEM INCLUDING THE SIGNAL RECEIVING DEVICE
    19.
    发明申请
    SIGNAL RECEIVING DEVICE, AND A SEMICONDUCTOR APPARATUS AND A SEMICONDUCTOR SYSTEM INCLUDING THE SIGNAL RECEIVING DEVICE 有权

    公开(公告)号：US20220006605A1

    公开(公告)日：2022-01-06

    申请号：US17478591

    申请日：2021-09-17

    Applicant: SK hynix Inc.

    Inventor： Soon Sung AN ,  Kwan Su SHON ,  Jin Ha HWANG

    IPC: H04L7/00 ,  H04L7/02

    Abstract: A signal receiving device may include a high-speed receiving circuit, a low-speed receiving circuit, a low-speed synchronization circuit and a low-speed synchronization circuit. The high-speed receiving circuit receives an input signal and generate a high-speed received signal in a first operation mode. The high-speed synchronization circuit generates a high-speed synchronized signal to synchronize the high-speed received signal with a clock signal. The low-speed receiving circuit receives the input signal and generate a low-speed received signal in a second operation mode. The low-speed synchronization circuit generates a low-speed synchronized signal to synchronize the low-speed received signal with the clock signal. According to an operation mode, one of the high-speed synchronized signal and the low-speed synchronized signal is selected as an internal signal.

    IMPEDANCE CALIBRATION CIRCUIT AND SEMICONDUCTOR APPARATUS INCLUDING THE SAME
    20.
    发明申请
    IMPEDANCE CALIBRATION CIRCUIT AND SEMICONDUCTOR APPARATUS INCLUDING THE SAME 有权

    公开(公告)号：US20210194485A1

    公开(公告)日：2021-06-24

    申请号：US16900537

    申请日：2020-06-12

    Applicant: SK hynix Inc.

    Inventor： Eun Ji CHOI ,  Jin Ha HWANG ,  Keun Seon AHN ,  Yo Han JEONG

    IPC: H03K19/00 ,  H03K19/0185

    Abstract: An impedance calibration circuit may include: a first driver having an impedance calibrated according to a first impedance control code, and configured to drive an output terminal according to first data; a second driver having an impedance calibrated according to a second impedance control code, and configured to drive the output terminal according to second data; and an impedance calibration circuit configured to calibrate the first impedance control code to a first target value set to a resistance value of an external resistor, and calibrate the second impedance control code to a second target value different from the resistance value of the external resistor.

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