公开(公告)号：US09136113B2

公开(公告)日：2015-09-15

申请号：US14044846

申请日：2013-10-02

Applicant: SOITEC

Inventor： Didier Landru ,  Fabrice Gritti ,  Eric Guiot ,  Oleg Kononchuk ,  Christelle Veytizou

IPC: H01L21/461 ,  H01L21/02 ,  H01L21/316 ,  H01L21/324 ,  H01L21/762

CPC classification number: H01L21/3247 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/02422 ,  H01L21/02532 ,  H01L21/31662 ,  H01L21/7624

Abstract: A process for avoiding formation of an Si—SiO2—H2 environment during a dissolution treatment of a semiconductor-on-insulator structure that includes a carrier substrate, an oxide layer, a thin layer of a semiconductor material and a peripheral ring in which the oxide layer is exposed. This process includes encapsulating at least the exposed oxide layer of the peripheral ring with semiconductor material by performing a creep thermal treatment; and performing an oxide dissolution treatment to reduce part of the thickness of the oxide layer. In this process, the semiconductor material that encapsulates the oxide layer has a thickness before the oxide dissolution that is at least twice that of the oxide that is to be dissolved, thus avoiding formation of an Si—SiO2—H2 environment on the peripheral ring where the oxide layer would otherwise be exposed.

Abstract translation: 在绝缘体上半导体结构的溶解处理中避免形成Si-SiO 2 -H 2环境的方法，其包括载体衬底，氧化物层，半导体材料的薄层和外围环，其中氧化物 层暴露。 该方法包括通过进行蠕变热处理将至少外围环的暴露的氧化物层与半导体材料封装起来; 并进行氧化物溶解处理以减少氧化物层的厚度的一部分。 在该方法中，封装氧化物层的半导体材料的氧化物溶解前的厚度为要溶解的氧化物的至少两倍，因此避免在外围环上形成Si-SiO 2 -H 2环境， 否则会暴露氧化层。

公开(公告)号：US12119258B2

公开(公告)日：2024-10-15

申请号：US17623499

申请日：2020-03-25

Applicant: COMMISSARIAT À L'ENERGIE ATOMIQUE ET AUX ÉNERGIES ALTERNATIVES ,  Soitec

Inventor： Emmanuel Augendre ,  Frédéric Gaillard ,  Thomas Lorne ,  Emmanuel Rolland ,  Christelle Veytizou ,  Isabelle Bertrand ,  Frédéric Allibert

IPC: H01L21/00 ,  H01L21/02 ,  H01L21/762 ,  H01L23/64

CPC classification number: H01L21/76254 ,  H01L21/02164 ,  H01L21/02203 ,  H01L23/64

Abstract: A semiconductor structure for radio frequency applications includes a support substrate made of silicon and comprising a mesoporous layer, a dielectric layer arranged on the mesoporous layer and a superficial layer arranged on the dielectric layer. The mesoporous layer comprises hollow pores, the internal walls of which are mainly lined with oxide. The mesoporous layer has a thickness between 3 and 40 microns and a resistivity greater than 20 kohm·cm over its entire thickness. The support substrate has a resistivity between 0.5 and 4 ohm·cm. The invention also relates to a method for producing such a semiconductor structure.

公开(公告)号：US11688627B2

公开(公告)日：2023-06-27

申请号：US16982986

申请日：2019-03-13

Applicant: Soitec

Inventor： Frederic Allibert ,  Christelle Veytizou ,  Damien Radisson

IPC: H01L21/762 ,  H01L23/29 ,  H01L23/31 ,  H01L23/373

CPC classification number: H01L21/76251 ,  H01L23/291 ,  H01L23/3171 ,  H01L23/3733

Abstract: A substrate for radiofrequency microelectronic devices comprises a carrier substrate made of a semi-conductor, a sintered composite layer disposed on the carrier substrate and formed from powders of at least a first dielectric material and a second dielectric different from the first material, the sintered composite layer having a thickness larger than 5 microns and a thermal expansion coefficient that is matched with that of the carrier substrate to plus or minus 30%.

公开(公告)号：US11373856B2

公开(公告)日：2022-06-28

申请号：US16476415

申请日：2018-01-11

Applicant: Soitec

Inventor： Patrick Reynaud ,  Marcel Broekaart ,  Frederic Allibert ,  Christelle Veytizou ,  Luciana Capello ,  Isabelle Bertrand

IPC: H01L29/66 ,  H01L21/8238 ,  H01L21/02 ,  H01L21/762

Abstract: A support for a semiconductor structure includes a base substrate, a first silicon dioxide insulating layer positioned on the base substrate and having a thickness greater than 20 nm, and a charge trapping layer having a resistivity higher than 1000 ohm·cm and a thickness greater than 5 microns positioned on the first insulating layer.

公开(公告)号：US20220076991A1

公开(公告)日：2022-03-10

申请号：US17416948

申请日：2019-12-19

Applicant: Soitec

Inventor： Kim Young Pil ,  Christelle Veytizou

IPC: H01L21/762 ,  H01L21/322 ,  H01L21/02 ,  H01L27/12

Abstract: A semiconductor-on-insulator substrate for radio-frequency applications, comprises: —a silicon carrier substrate, —an electrically insulating layer arranged on the carrier substrate, —a single-crystal layer arranged on the electrically insulating layer, the substrate being characterized in that it further comprises a layer of silicon carbide SiC arranged between the carrier substrate and the electrically insulating layer, which has a thickness between 1 nm and 5 nm, the surface of the layer of silicon carbide SiC that is on the side of the electrically insulating layer being rough.

公开(公告)号：US20200020520A1

公开(公告)日：2020-01-16

申请号：US16476415

申请日：2018-01-11

Applicant: Soitec

Inventor： Patrick Reynaud ,  Marcel Broekaart ,  Frederic Allibert ,  Christelle Veytizou ,  Luciana Capello ,  Isabelle Bertrand

IPC: H01L21/02 ,  H01L21/762

Abstract: A support for a semiconductor structure includes a base substrate, a first silicon dioxide insulating layer positioned on the base substrate and having a thickness greater than 20 nm, and a charge trapping layer having a resistivity higher than 1000 ohm·cm and a thickness greater than 5 microns positioned on the first insulating layer.