公开(公告)号：US20240387243A1

公开(公告)日：2024-11-21

申请号：US18688606

申请日：2022-10-19

Applicant: Soitec

Inventor： Youngpil Kim ,  Oleg Kononchuk ,  Chee Hoe Wong

IPC: H01L21/763 ,  H01L21/762 ,  H10N30/072

Abstract: A method for preparing a support substrate having a charge-trapping layer includes introducing a monocrystalline silicon base substrate into a chamber of deposition equipment and, without removing the base substrate from the chamber and while flushing the chamber with a carrier gas, performing the following successive steps: forming a dielectric layer on the base substrate by introducing a reactive gas into the chamber over a first time period; and forming a polycrystalline silicon charge-trapping layer directly on the dielectric layer by introducing a precursor gas containing silicon into the chamber over a second time period, subsequent to the first time period. The time for which the dielectric layer is exposed only to the carrier gas, between the first time period and the second time period, is less than 30 seconds and the formation of the charge-trapping layer is performed at a temperature strictly between 1010° C. and 1200° C.

公开(公告)号：US12143093B2

公开(公告)日：2024-11-12

申请号：US18352972

申请日：2023-07-14

Applicant: Soitec

Inventor： Marcel Broekaart ,  Thierry Barge ,  Pascal Guenard ,  Ionut Radu ,  Eric Desbonnets ,  Oleg Kononchuk

IPC: H03H9/02 ,  A61B5/00 ,  A61B5/145 ,  A61B5/1459 ,  H03H3/02 ,  H03H3/04 ,  H03H3/10 ,  H03H9/13 ,  H03H9/145 ,  H03H9/17 ,  H03H9/25 ,  H03H9/56 ,  H03H9/64 ,  H10N30/072 ,  H10N30/085 ,  H10N30/87 ,  H10N39/00

Abstract: A substrate for a surface acoustic wave device or bulk acoustic wave device, comprising a support substrate and an piezoelectric layer on the support substrate, wherein the support substrate comprises a semiconductor layer on a stiffening substrate having a coefficient of thermal expansion that is closer to the coefficient of thermal expansion of the material of the piezoelectric layer than that of silicon, the semiconductor layer being arranged between the piezoelectric layer and the stiffening substrate.

公开(公告)号：US20220157650A1

公开(公告)日：2022-05-19

申请号：US17435631

申请日：2020-02-26

Applicant: Soitec

Inventor： Didier Landru ,  Oleg Kononchuk ,  Nadia Ben Mohamed

IPC: H01L21/762

Abstract: A method for transferring a useful layer to a carrier substrate comprises: joining a front face of a donor substrate to a carrier substrate along a bonding interface to form a bonded structure; annealing the bonded structure to apply a weakening thermal budget thereto and bring a buried weakened plane in the donor substrate to a defined level of weakening, the anneal reaching a maximum hold temperature; and initiating a self-sustained and propagating splitting wave in the buried weakened plane by applying a stress to the bonded structure to lead to the useful layer being transferred to the carrier substrate. The initiation of the splitting wave occurs when the bonded structure experiences a thermal gradient defining a hot region and a cool region of the bonded structure, the stress being applied locally in the cool region, and the hot region experiencing a temperature lower than the maximum hold temperature.

公开(公告)号：US20210050249A1

公开(公告)日：2021-02-18

申请号：US16969346

申请日：2019-01-14

Applicant: Soitec

Inventor： Didier Landru ,  Oleg Kononchuk ,  Nadia Ben Mohamed ,  Rénald Guerin ,  Norbert Colombet

IPC: H01L21/762

Abstract: A detachable structure comprises a carrier substrate and a silicon oxide layer positioned on the substrate at a first interface. The detachable structure is notable in that: the oxide layer has a thickness of less than 200 nm; light hydrogen and/or helium species are distributed deeply and over the entire area of the structure according to an implantation profile, a maximum concentration of which is located in the thickness of the oxide layer; the total dose of implanted light species, relative to the thickness of the oxide layer, exceeds, at least by a factor of five, the solubility limit of these light species in the oxide layer.

公开(公告)号：US20200228088A1

公开(公告)日：2020-07-16

申请号：US16829604

申请日：2020-03-25

Applicant: Soitec

Inventor： Marcel Broekaart ,  Thierry Barge ,  Pascal Guenard ,  Ionut Radu ,  Eric Desbonnets ,  Oleg Kononchuk

IPC: H03H9/02 ,  H01L41/312 ,  H03H3/02 ,  H01L27/20 ,  H01L41/047 ,  H03H3/04 ,  H03H3/10 ,  H03H9/13 ,  H03H9/145 ,  H03H9/17 ,  H03H9/25 ,  H03H9/56 ,  H03H9/64

Abstract: A substrate for a surface acoustic wave device or bulk acoustic wave device, comprising a support substrate and an piezoelectric layer on the support substrate, wherein the support substrate comprises a semiconductor layer on a stiffening substrate having a coefficient of thermal expansion that is closer to the coefficient of thermal expansion of the material of the piezoelectric layer than that of silicon, the semiconductor layer being arranged between the piezoelectric layer and the stiffening substrate.

公开(公告)号：US20200054978A1

公开(公告)日：2020-02-20

申请号：US16341390

申请日：2017-09-21

Applicant: Soitec

Inventor： Didier Landru ,  Oleg Kononchuk

IPC: B01D46/00

Abstract: A vertical furnace includes a chamber intended for receiving a loading column an inlet channel for fresh gas, arranged at an upper end of the chamber, the loading column comprising an upper portion, and a central portion for supporting a plurality of substrates. The vertical furnace further comprises a trapping device made of at least one material suitable for trapping all or part of the contaminants present in the fresh gas. The trapping device includes a circular part arranged on the upper part of the loading column, the circular part comprising fins regularly distributed over an upper surface of the circular part in order to increase the contact surface of the trapping device with the fresh gas.

公开(公告)号：US10250282B2

公开(公告)日：2019-04-02

申请号：US15531976

申请日：2015-09-17

Applicant: Soitec

Inventor： Oleg Kononchuk ,  Didier Landru ,  Christophe Figuet

IPC: H04B1/38 ,  H04B1/03 ,  H01L21/02 ,  H01L21/762 ,  H01M4/66 ,  H01L21/28 ,  H01L41/047

Abstract: A structure for radiofrequency applications includes: a semiconducting supporting substrate, and a trapping layer arranged on the supporting substrate. The trapping layer includes a higher defect density than a predetermined defect density. The predetermined defect density is the defect density beyond which the electric resistivity of the trapping layer is no lower than 10,000 ohm·cm over a temperature range extending from −20° C. to 120° C.

公开(公告)号：US20180102264A1

公开(公告)日：2018-04-12

申请号：US15728953

申请日：2017-10-10

Applicant: Soitec

Inventor： Didier Landru ,  Oleg Kononchuk ,  Sébastien Simon

IPC: H01L21/67 ,  H01L21/677 ,  F27D7/06 ,  F27D5/00

Abstract: A thermal treatment system includes a chamber capable of receiving a plurality of substrates, a gas intake path in a distal portion of the chamber located opposite an area for entry of substrates into the chamber, and an outlet path for the gas and/or volatile species generated during the thermal treatment. The outlet path is located in a proximal portion of the chamber located near the area for entry of the substrates into the chamber. The system further includes a collector device in the proximal portion of the chamber. The collector device has a confinement opening oriented toward the distal portion of the chamber, and the collector device defines a compartment communicating with the outlet path, the compartment being configured so that the gas and the volatile species enter into the compartment via the confinement opening and pass through the compartment to reach the outlet path.

公开(公告)号：US09396987B2

公开(公告)日：2016-07-19

申请号：US14369594

申请日：2012-12-21

Applicant: Soitec

Inventor： Oleg Kononchuk

IPC: H01L21/02 ,  H01L21/762 ,  H01L21/18 ,  H01L21/265 ,  H01L21/683

CPC classification number: H01L21/76254 ,  H01L21/187 ,  H01L21/265 ,  H01L21/6836

Abstract: The invention relates to a method for fabricating a substrate, comprising the steps of providing a donor substrate with at least one free surface, performing an ion implantation at a predetermined depth of the donor substrate to form an in-depth predetermined splitting area inside the donor substrate, and is characterized in providing a layer of an adhesive, in particular an adhesive paste, over the at least one free surface of the donor substrate. The invention further relates to a semiconductor structure comprising a semiconductor layer, and a layer of a ceramic-based and/or a graphite-based and/or a metal-based adhesive provided on one main side of the semiconductor layer.

Abstract translation: 本发明涉及一种用于制造衬底的方法，包括以下步骤：向供体衬底提供至少一个自由表面，在供体衬底的预定深度处进行离子注入，以在供体内形成深入的预定分裂区域 衬底，并且其特征在于在施主衬底的至少一个自由表面上提供粘合剂层，特别是粘合剂糊剂层。 本发明还涉及一种半导体结构，其包括半导体层，以及设置在半导体层的一个主侧上的基于陶瓷的和/或基于石墨的和/或金属基粘合剂层。

公开(公告)号：US20150364364A1

公开(公告)日：2015-12-17

申请号：US14377738

申请日：2013-01-28

Applicant: SOITEC

Inventor： Gweltaz Gaudin ,  Oleg Kononchuk ,  Ionut Radu

IPC: H01L21/762 ,  B32B7/04 ,  B32B9/04

CPC classification number: H01L21/76254 ,  B32B7/04 ,  B32B9/04 ,  B32B2457/14 ,  Y10T428/24802

Abstract: A method comprising the following steps: providing a support substrate and a donor substrate, forming an embrittlement region in the donor substrate so as to delimit a first portion and a second portion on either side of the embrittlement region, assembling the donor substrate on the support substrate, fracturing the donor substrate along the embrittlement. In addition, the method comprises a step consisting of forming a compressive stress layer in the donor substrate so as to delimit a so-called confinement region interposed between the compressive stress layer and the embrittlement region.

Abstract translation: 一种包括以下步骤的方法：提供支撑衬底和供体衬底，在所述供体衬底中形成脆化区域，以限定所述脆化区域的任一侧上的第一部分和第二部分，将所述施主衬底组装在所述支撑体上 底物，沿着脆化破坏施主衬底。 此外，该方法包括在施主衬底中形成压应力层以限定介于压应力层和脆化区之间的所谓约束区的步骤。