公开(公告)号：US20190035784A1

公开(公告)日：2019-01-31

申请号：US16046683

申请日：2018-07-26

Applicant: STMICROELECTRONICS (ROUSSET) SAS

Inventor： Franck JULIEN

IPC: H01L27/088 ,  H01L27/12 ,  H01L21/84 ,  H01L21/8236

Abstract: The disclosure relates to a method of simultaneous fabrication of an MOS transistor of SOI type, and of first and second transistors on bulk substrate, comprising: a) providing a semiconductor layer on an insulating layer covering a semiconductor substrate; b) forming a mask comprising, above the location of the second transistor, a central opening which is less wide than the second transistor to be formed; c) plumb with the opening, entirely etching the semiconductor layer and insulating layer, hence resulting in remaining portions of the insulating layer at the location of the second transistor; d) growing the semiconductor by epitaxy as far as the upper level of the semiconductor layer; e) forming isolating trenches; and f) forming the gate insulators of the transistors, the gate insulator of the second transistor comprising at least one part of the said remaining portions of the insulating layer.

公开(公告)号：US20240074134A1

公开(公告)日：2024-02-29

申请号：US18230952

申请日：2023-08-07

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Paul DEVOGE ,  Abderrezak MARZAKI ,  Franck JULIEN ,  Alexandre MALHERBE

IPC: H10B10/00 ,  H01L29/66 ,  H01L29/788

CPC classification number: H10B10/12 ,  H01L29/66825 ,  H01L29/788

Abstract: An integrated circuit includes transistor. That transistor is manufactured using a process including the following steps: forming a first gate region; depositing dielectric layers accumulating on sides of the first gate region to form regions of spacers having a width; etching to remove a part of the deposited dielectric layers accumulated on the sides of the first gate region to reduce the width of the regions of spacers; performing a first implantation of dopants aligned on the regions of spacers to form first lightly doped conduction regions of the transistor; and performing a second implanting of dopants to form first more strongly doped conduction regions of the transistor.

公开(公告)号：US20230238272A1

公开(公告)日：2023-07-27

申请号：US18127751

申请日：2023-03-29

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Franck JULIEN ,  Abderrezak MARZAKI

IPC: H01L21/762 ,  H01L21/02 ,  H01L21/306 ,  H01L21/308 ,  H01L21/311 ,  H01L25/16 ,  H01L25/18

CPC classification number: H01L21/76224 ,  H01L21/0217 ,  H01L21/30625 ,  H01L21/308 ,  H01L21/31116 ,  H01L25/16 ,  H01L25/18

Abstract: Trenches of different depths in an integrated circuit are formed by a process utilizes a dry etch. A first stop layer is formed over first and second zones of the substrate. A second stop layer is formed over the first stop layer in only the second zone. A patterned mask defines the locations where the trenches are to be formed. The dry etch uses the mask to etch in the first zone, in a given time, through the first stop layer and then into the substrate down to a first depth to form a first trench. This etch also, at the same time, etch in the second zone through the second stop layer, and further through the first stop layer, and then into the substrate down to a second depth to form a second trench. The second depth is shallower than the first depth.

公开(公告)号：US20220139782A1

公开(公告)日：2022-05-05

申请号：US17516857

申请日：2021-11-02

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Franck JULIEN

IPC: H01L21/8234 ,  H01L21/306 ,  H01L21/266 ,  H01L21/308 ,  H01L29/66

Abstract: An integrated circuit includes metal-oxide-semiconductor “MOS” transistors formed on a semiconductor substrate. The MOS transistors have gate stacks belonging to at least one gate stack category and dielectric regions of sidewall spacers on the sides of the gate stacks. At least a first MOS transistor has a gate stack of said at least one gate stack category that includes dielectric regions of sidewall spacers having a first width. At least a second MOS transistor has a gate stack of the same gate stack category with dielectric regions of sidewall spacers having a second width different from the first width.

公开(公告)号：US20210118725A1

公开(公告)日：2021-04-22

申请号：US17068112

申请日：2020-10-12

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Franck JULIEN ,  Abderrezak MARZAKI

IPC: H01L21/762 ,  H01L21/308 ,  H01L21/311 ,  H01L21/306 ,  H01L21/02 ,  H01L25/18 ,  H01L25/16

Abstract: Trenches of different depths in an integrated circuit are formed by a process utilizes a dry etch. A first stop layer is formed over first and second zones of the substrate. A second stop layer is formed over the first stop layer in only the second zone. A patterned mask defines the locations where the trenches are to be formed. The dry etch uses the mask to etch in the first zone, in a given time, through the first stop layer and then into the substrate down to a first depth to form a first trench. This etch also, at the same time, etch in the second zone through the second stop layer, and further through the first stop layer, and then into the substrate down to a second depth to form a second trench. The second depth is shallower than the first depth.

公开(公告)号：US20210035996A1

公开(公告)日：2021-02-04

申请号：US16939603

申请日：2020-07-27

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Franck JULIEN ,  Abderrezak MARZAKI

IPC: H01L27/11531 ,  H01L27/11521 ,  H01L29/788 ,  H01L21/02 ,  H01L21/311 ,  H01L21/265 ,  H01L21/28 ,  H01L29/66

Abstract: A process for fabricating an integrated circuit includes the fabrication of a first transistor and a floating-gate transistor. The fabrication process for the first transistor and the floating-gate transistor utilizes a common step of forming a dielectric layer. This dielectric layer is configured to form a tunnel-dielectric layer of the floating-gate transistor (which allows transfer of charge via the Fowler-Nordheim effect) and to form a gate-dielectric layer of the first transistor.