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公开(公告)号：US20210409032A1
公开(公告)日：2021-12-30
申请号：US17354126
申请日：2021-06-22
Applicant: STMicroelectronics International N.V.
Inventor： Ankur BAL , Vikram SINGH
IPC: H03M1/10
Abstract: A time-interleaved analog to digital converter (TI-ADC) includes a first sub-ADC configured to sample and convert an input analog signal to generate a first digital signal and a second sub-ADC configured to sample and convert said input analog signal to generate a second digital signal. Sampling by the second sub-ADC occurs with a time skew mismatch. A multiplexor interleaves the first and second digital signals to generate a third digital signal. A time skew mismatch error determination circuit processes the first and second digital signals to generate a time error corresponding to the time skew mismatch. A slope value of said third digital signal is determined and multiplied by the time error to generate a signal error. The signal error is summed with the third digital signal to generate a digital output signal which eliminates the error due to the time skew mismatch. This correction is performed in real time.
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公开(公告)号：US20210286417A1
公开(公告)日：2021-09-16
申请号：US17194037
申请日：2021-03-05
Applicant: STMICROELECTRONICS INTERNATIONAL N.V.
Inventor： Ankur BAL , Vikas CHELANI
Abstract: An integrated circuit includes a plurality of flip-flops and a global reset network for resetting the flip-flops. The integrated circuit includes a synchronous clock delay circuit that delays, responsive to a global reset signal, a transition in a clock signal provided to the flip-flops. The delay in the transition of the clock signal ensures that all of the flip-flops receive the global reset signal within a same delayed clock cycle and that the flip-flops do not receive the global reset signal during a rising or falling edge of the clock signal.
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公开(公告)号：US20240192314A1
公开(公告)日：2024-06-13
申请号：US18521570
申请日：2023-11-28
Applicant: STMicroelectronics International N.V.
Inventor： Ankur BAL , Vikram SINGH
IPC: G01S7/35
CPC classification number: G01S7/35
Abstract: An apparatus, method, and system for efficiently storing proportional data is provided. An example apparatus may include a controller configured to determine a linear estimate based on input values provided to a first circuit and proportional output values received from the first circuit. The input values include a first input value proportional to a first output value and a second input value proportional to a second output value. Further, the linear estimate of the output values may be determined based on the first output value and a linear rate of change, wherein the linear rate of change corresponds to the change from the first input value to the second input value and the change from the first output value to the second output value. The apparatus may further comprise a memory, configured to store a storage value that represents an offset of an output value from the linear estimate.
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公开(公告)号：US20230251829A1
公开(公告)日：2023-08-10
申请号：US18134737
申请日：2023-04-14
Applicant: STMicroelectronics International N.V.
Inventor： Ankur BAL , Rupesh SINGH
CPC classification number: G06F7/548 , H03K3/037 , G06F7/5443 , H03K5/01 , H03K2005/00078
Abstract: A first multiplier multiplies a first input with a first coefficient and a first adder sums an output of the first multiplier and a second input to generate a first output. A second multiplier multiplies a third input with a second coefficient, a third multiplier multiplies a fourth input with a third coefficient, and a second adder sums outputs of the second and third multipliers to generate a second output. The second and third inputs are derived from the first output and the first and fourth inputs are derived from the second output. The first and second outputs generate digital values for first and second digital sinusoids, respectively.
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公开(公告)号：US20230061509A1
公开(公告)日：2023-03-02
申请号：US17876263
申请日：2022-07-28
Applicant: STMicroelectronics International N.V.
Inventor： Sharad GUPTA , Ankur BAL
IPC: H03M1/06
Abstract: A data weighted averaging (DWA) data word in a standard or normal form unary code format is first converted to a thermometer control word in an alternative or spatial form unary code format. The thermometer control word is then converted from the alternative or spatial form unary code format to output a corresponding binary word.
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Patent Agency Ranking
公开(公告)号：US20220069837A1
公开(公告)日：2022-03-03
申请号：US17374351
申请日：2021-07-13
Applicant: STMicroelectronics International N.V.
Inventor： Ankur BAL , Rupesh SINGH
Abstract: A latch circuit sequentially latches a first data weighted averaging (DWA) data word and then a second DWA data word. A first detector circuit identifies a first bit location in the first DWA data that is associated with an ending of a first string of logic 1 bits in the first DWA data word. A second detector circuit identifies a second bit location in the second DWA data word associated with an ending of a second string of logic 1 bits in the second DWA data word. A DWA-to-binary conversion circuit converts the second DWA data word to a binary word by using the first bit location and second bit location to identify a number of logic 1 bits present in said second DWA data word. A binary value for that binary word that is equal to the identified number is output.
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公开(公告)号：US20210081174A1
公开(公告)日：2021-03-18
申请号：US16988912
申请日：2020-08-10
Applicant: STMicroelectronics International N.V.
Inventor： Ankur BAL , Rupesh SINGH
Abstract: A first multiplier multiplies a first input with a first coefficient and a first adder sums an output of the first multiplier and a second input to generate a first output. A second multiplier multiplies a third input with a second coefficient, a third multiplier multiplies a fourth input with a third coefficient, and a second adder sums outputs of the second and third multipliers to generate a second output. The second and third inputs are derived from the first output and the first and fourth inputs are derived from the second output. The first and second outputs generate digital values for first and second digital sinusoids, respectively.
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公开(公告)号：US20140241539A1
公开(公告)日：2014-08-28
申请号：US14271128
申请日：2014-05-06
Applicant: STMicroelectronics International N.V.
Inventor： Ankur BAL , Anupam JAIN , Rakhel Kumar PARIDA
IPC: G10K11/00
CPC classification number: G10K11/002 , G10L21/0208 , G10L21/0232 , H04L5/0008 , H04L25/03159 , H04L27/2649 , H04L2025/03414
Abstract: A system for noise removal is coupled to a signal unit that provides a digital signal. The noise removal system includes a transformation module to transform the digital signal into an f-digital signal, a threshold filter to generate a noiseless signal from the f-digital signal based on a threshold profile, and a signal synthesizer to provide a gain to the noiseless signal and to transform the noiseless signal into an output signal.
Abstract translation: 用于噪声去除的系统耦合到提供数字信号的信号单元。 噪声去除系统包括：将数字信号变换为f数字信号的变换模块，基于阈值分布的f数字信号产生无噪声信号的阈值滤波器;以及信号合成器，用于向 并将无噪声信号变换为输出信号。
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公开(公告)号：US20250068538A1
公开(公告)日：2025-02-27
申请号：US18766904
申请日：2024-07-09
Applicant: STMicroelectronics International N.V.
Inventor： Sharad GUPTA , Ankur BAL
Abstract: Various embodiments of the present disclosure disclose improved BIST systems and methods for testing digital devices. A method for testing a digital device includes receiving, based at least in part on an input signal, an output signal from a device under testing (DUT). The output signal is processed to generate a noise signal and a recovered signal for the DUT. The controller may generate a signal to noise power ratio based at least in part on the noise and recovered signals and compare the signal to noise power ratio to a predetermined power threshold to generate a performance metric.
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公开(公告)号：US20240146324A1
公开(公告)日：2024-05-02
申请号：US18482333
申请日：2023-10-06
Applicant: STMicroelectronics International N.V.
Inventor： Ankur BAL , Anubhuti CHOPRA
IPC: H03M1/10
CPC classification number: H03M1/1028 , H03M1/1038
Abstract: Offset calibration for an analog front-end system is provided. The analog front-end system includes a variable-gain amplifier, and the calibration mitigates an offset error of the variable-gain amplifier. Calibration is based on a difference-based estimation technique combined with digital iteration. Difference-based estimation includes measuring different digital output signals from an analog-to-digital converter for different respective gains of the variable-gain amplifier. The digital iteration is utilized to estimate offsets values which converge a digital output difference to a target of zero volts.
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