公开(公告)号：US20220139453A1

公开(公告)日：2022-05-05

申请号：US17578086

申请日：2022-01-18

Applicant: STMICROELECTRONICS INTERNATIONAL N.V.

Inventor： Nitin CHAWLA ,  Tanmoy ROY ,  Anuj GROVER

IPC: G11C13/00 ,  G06F9/50 ,  G06N3/063 ,  G11C29/00 ,  G11C29/26

Abstract: A memory management circuit stores information indicative of reliability-types of regions of a memory array. The memory management circuitry responds to a request to allocate memory in the memory array to a process by determining a request type associated with the request to allocate memory. Memory of the memory array is allocated to the process based on the request type associated with the request to allocate memory and the stored information indicative of reliability-types of regions of the memory array. The memory array may be a shared memory array. The memory array may be organized into rows and columns, and the regions of the memory array may be the rows of the memory array.

公开(公告)号：US20210081773A1

公开(公告)日：2021-03-18

申请号：US17023144

申请日：2020-09-16

Applicant: STMICROELECTRONICS S.r.l. ,  STMicroelectronics International N.V.

Inventor： Nitin CHAWLA ,  Giuseppe DESOLI ,  Manuj AYODHYAWASI ,  Thomas BOESCH ,  Surinder Pal SINGH

IPC: G06N3/063 ,  G06F1/08 ,  G06F1/324 ,  G06F9/50 ,  G06N3/08 ,  G06F1/3228 ,  G06F1/3296

Abstract: Systems and devices are provided to increase computational and/or power efficiency for one or more neural networks via a computationally driven closed-loop dynamic clock control. A clock frequency control word is generated based on information indicative of a current frame execution rate of a processing task of the neural network and a reference clock signal. A clock generator generates the clock signal of neural network based on the clock frequency control word. A reference frequency may be used to generate the clock frequency control word, and the reference frequency may be based on information indicative of a sparsity of data of a training frame.

公开(公告)号：US20250069678A1

公开(公告)日：2025-02-27

申请号：US18939751

申请日：2024-11-07

Applicant: STMicroelectronics International N.V.

Inventor： Hitesh CHAWLA ,  Tanuj KUMAR ,  Bhupender SINGH ,  Harsh RAWAT ,  Kedar Janardan DHORI ,  Manuj AYODHYAWASI ,  Nitin CHAWLA ,  Promod KUMAR

IPC: G11C29/12 ,  G11C29/36

Abstract: The memory array of a memory includes sub-arrays with memory cells arranged in a row-column matrix where each row includes a word line and each sub-array column includes a local bit line. A row decoder circuit supports two modes of memory circuit operation: a first mode where only one word line in the memory array is actuated during a memory read and a second mode where one word line per sub-array are simultaneously actuated during the memory read. An input/output circuit for each column includes inputs to the local bit lines of the sub-arrays, a column data output coupled to the bit line inputs, and a sub-array data output coupled to each bit line input. Both BIST and ATPG testing of the input/output circuit are supported. For BIST testing, multiple data paths between the bit line inputs and the column data output are selectively controlled to provide complete circuit testing.

公开(公告)号：US20230102492A1

公开(公告)日：2023-03-30

申请号：US17954060

申请日：2022-09-27

Applicant: STMicroelectronics International N.V.

Inventor： Harsh RAWAT ,  Kedar Janardan DHORI ,  Promod KUMAR ,  Nitin CHAWLA ,  Manuj AYODHYAWASI

IPC: G11C7/10 ,  G11C7/12

Abstract: A memory array includes a plurality of bit-cells arranged as a set of rows of bit-cells intersecting a plurality of columns. The memory array also includes a plurality of in-memory-compute (IMC) cells arranged as a set of rows of IMC cells intersecting the plurality of columns of the memory array. Each of the IMC cells of the memory array includes a first bit-cell having a latch, a write-bit line and a complementary write-bit line, and a second bit-cell having a latch, a write-bit line and a complementary write-bit line, wherein the write-bit line of the first bit-cell is coupled to the complementary write-bit line of the second bit-cell and the complementary write-bit line of the first bit-cell is coupled to the write-bit line of the second bit-cell.

公开(公告)号：US20230012303A1

公开(公告)日：2023-01-12

申请号：US17852567

申请日：2022-06-29

Applicant: STMicroelectronics International N.V.

Inventor： Kedar Janardan DHORI ,  Harsh RAWAT ,  Promod KUMAR ,  Nitin CHAWLA ,  Manuj AYODHYAWASI

IPC: G11C11/418 ,  G11C11/412 ,  G11C11/419

Abstract: A circuit includes a memory array with SRAM cells connected in rows by word lines and in columns by bit lines. A row controller circuit simultaneously actuates, through a word line driver circuit for each row, word lines in parallel for an in-memory compute operation. A column processing circuit processes analog voltages developed on the bit lines in response to the simultaneous actuation to generate a decision output for the in-memory compute operation. A bit line clamping circuit includes a sensing circuit that compares the analog voltages on a given pair of bit lines to a threshold voltage. A voltage clamp circuit is actuated in response to the comparison to preclude the analog voltages on the given pair of bit lines from decreasing below a clamping voltage level.

公开(公告)号：US20230008275A1

公开(公告)日：2023-01-12

申请号：US17844434

申请日：2022-06-20

Applicant: STMicroelectronics International N.V.

Inventor： Kedar Janardan DHORI ,  Nitin CHAWLA ,  Promod KUMAR ,  Manuj AYODHYAWASI ,  Harsh RAWAT

IPC: G11C11/408 ,  G11C11/4076 ,  G11C11/4074 ,  G11C7/04 ,  H03K19/17728

Abstract: An in-memory computation circuit includes a memory array with SRAM cells connected in rows by word lines and in columns by bit lines. Each row includes a word line drive circuit powered by an adaptive supply voltage. A row controller circuit simultaneously actuates word lines in parallel for an in-memory compute operation. A column processing circuit processes analog voltages developed on the bit lines in response to the simultaneous actuation to generate a decision output for the in-memory compute operation. A voltage generator circuit generates the adaptive supply voltage for powering the word line drive circuits during the simultaneous actuation. A level of the adaptive supply voltage is modulated dependent on integrated circuit process and/or temperature conditions in order to optimize word line underdrive performance and inhibit unwanted memory cell data flip.

公开(公告)号：US20230004354A1

公开(公告)日：2023-01-05

申请号：US17940654

申请日：2022-09-08

Applicant: STMICROELECTRONICS S.R.L. ,  STMICROELECTRONICS INTERNATIONAL N.V.

Inventor： Nitin CHAWLA ,  Tanmoy ROY ,  Anuj GROVER ,  Giuseppe DESOLI

IPC: G06F7/57 ,  G06F3/06 ,  G06N3/063

Abstract: A memory array arranged in multiple columns and rows. Computation circuits that each calculate a computation value from cell values in a corresponding column. A column multiplexer cycles through multiple data lines that each corresponds to a computation circuit. Cluster cycle management circuitry determines a number of multiplexer cycles based on a number of columns storing data of a compute cluster. A sensing circuit obtains the computation values from the computation circuits via the column multiplexer as the column multiplexer cycles through the data lines. The sensing circuit combines the obtained computation values over the determined number of multiplexer cycles. A first clock may initiate the multiplexer to cycle through its data lines for the determined number of multiplexer cycles, and a second clock may initiate each individual cycle. The multiplexer or additional circuitry may be utilized to modify the order in which data is written to the columns.

公开(公告)号：US20210181828A1

公开(公告)日：2021-06-17

申请号：US17111373

申请日：2020-12-03

Applicant: STMICROELECTRONICS S.r.l. ,  STMicroelectronics International N.V.

Inventor： Nitin CHAWLA ,  Anuj GROVER ,  Giuseppe DESOLI ,  Kedar Janardan DHORI ,  Thomas BOESCH ,  Promod KUMAR

IPC: G06F1/3234 ,  G11C11/413 ,  G05F3/24 ,  G06F1/3287 ,  G06F15/78

Abstract: Systems and devices are provided to enable granular control over a retention or active state of each of a plurality of memory circuits, such as a plurality of memory cell arrays, within a memory. Each respective memory array of the plurality of memory arrays is coupled to a respective ballast driver and a respective active memory signal switch for the respective memory array. One or more voltage regulators are coupled to a ballast driver gate node and to a bias node of at least one of the respective memory arrays. In operation, the respective active memory signal switch for a respective memory array causes the respective memory array to transition between an active state for the respective memory array and a retention state for the respective memory array.

公开(公告)号：US20240143239A1

公开(公告)日：2024-05-02

申请号：US18379373

申请日：2023-10-12

Applicant: STMicroelectronics International N.V.

Inventor： Bhupender SINGH ,  Hitesh CHAWLA ,  Tanuj KUMAR ,  Harsh RAWAT ,  Kedar Janardan DHORI ,  Promod KUMAR ,  Manuj AYODHYAWASI ,  Nitin CHAWLA

IPC: G06F3/06

CPC classification number: G06F3/0673 ,  G06F3/061 ,  G06F3/0655

Abstract: A memory circuit includes an array of memory cells arranged in rows and columns. A word line is connected to the memory cells of each row. A row decoder circuit operates in response to an internal clock and an address to selectively apply a word line signal to one word line and further generate a dummy word line signal. A control circuit includes a clock generator that generates the internal clock which is reset in response to a reset signal. A first delay circuit receives the dummy word line signal and outputs a first delayed dummy word line signal. A second delay circuit receives the dummy word line signal and outputs a second delayed dummy word line signal. A multiplexer circuit selects between the first and second delayed dummy word line signals for output as the reset signal in response to a logic state of a mode control signal.

公开(公告)号：US20230410892A1

公开(公告)日：2023-12-21

申请号：US18137261

申请日：2023-04-20

Applicant: STMicroelectronics International N.V.

Inventor： Kedar Janardan DHORI ,  Promod KUMAR ,  Nitin CHAWLA ,  Harsh RAWAT ,  Manuj AYODHYAWASI

IPC: G11C11/4096 ,  G11C11/408 ,  G11C11/4074 ,  G11C11/4094

CPC classification number: G11C11/4096 ,  G11C11/4094 ,  G11C11/4074 ,  G11C11/4085

Abstract: An in-memory computation circuit includes a memory array with SRAM cells connected in rows by word lines and in columns by bit lines. A row controller circuit simultaneously actuates word lines in parallel for an in-memory compute operation. A column processing circuit includes a current mirroring circuit that mirrors the read current developed on each bit line in response to the simultaneous actuation to generate a decision output for the in-memory compute operation. A bias voltage for word line driver and a configuration of the current mirroring circuit to inhibit drop of a voltage on the bit line below a bit flip voltage during execution of the in-memory compute operation. The mirrored read current is integrated by an integration capacitor to generate an output voltage that is converted to a digital signal by an analog-to-digital converter circuit.