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公开(公告)号：US09167023B2
公开(公告)日：2015-10-20
申请号：US14078118
申请日：2013-11-12
Applicant: STMicroelectronics International N.V.
Inventor： Surinder Pal Singh , Kaushik Saha
IPC: G01R19/18 , H04L29/08 , G01R21/133 , G01R19/22 , H04L12/24
CPC classification number: H04L67/025 , G01R19/22 , G01R21/133 , H04L41/32
Abstract: A system for power measurement in an electronic device includes a sensing unit, an analog-to-digital converter (ADC) and a controller. The sensing unit senses voltage across a power source and modulates a carrier signal based on the sensed voltage. The ADC converts a combination of the modulated carrier signal and audio signals received by the electronic device to generate a digitized combined signal and provides the digitized combined signal to the controller. The controller separates digitized modulated carrier signal and digitized audio signals. The digitized modulated carrier signal is demodulated to generate an output signal that provides a measure of the power consumed by the electronic device.
Abstract translation: 电子设备中的功率测量系统包括感测单元，模数转换器（ADC）和控制器。 感测单元感测电源两端的电压，并根据检测到的电压调制载波信号。 ADC转换由电子设备接收的调制载波信号和音频信号的组合，以产生数字化的组合信号，并将数字化的组合信号提供给控制器。 控制器分离数字化调制载波信号和数字化音频信号。 数字化调制载波信号被解调以产生提供电子设备消耗的功率的量度的输出信号。
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公开(公告)号：US08942502B2
公开(公告)日：2015-01-27
申请号：US13963860
申请日：2013-08-09
Applicant: STMicroelectronics International N.V.
Inventor： Surinder Pal Singh , Aneesh Bhasin , Kaushik Saha
Abstract: Parallelization of decoding of a data stream encoded with a variable length code includes determining one or more markers, each of which indicates a position within the encoded data stream. The determined markers are included into the encoded data stream together with the encoded data. At the decoder side, the markers are parsed from the encoded data stream and based on the extracted markers. The encoded data is separated into partitions, which are decoded separately and in parallel.
Abstract translation: 用可变长度码编码的数据流的解码的并行化包括确定一个或多个标记，每个标记表示编码数据流内的位置。 所确定的标记与编码数据一起被包括在编码数据流中。 在解码器侧，从编码数据流中解析出标记，并根据提取的标记进行解析。 编码数据被分成分开并且并行解码的分区。
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13.发明申请公开(公告)号：US20140055438A1
公开(公告)日：2014-02-27
申请号：US14069026
申请日：2013-10-31
Applicant: STMicroelectronics International N.V.
Inventor： Surinder Pal Singh , Kaushik Saha , Sumit Johar
IPC: G09G5/00
Abstract: An image processing arrangement includes an input to receive an indicator of a power characteristic related to an image processing arrangement and an image processor to process an image based on the indicator of the power characteristic.
Abstract translation: 图像处理装置包括用于接收与图像处理装置相关的功率特性的指示符的输入和基于功率特性的指标来处理图像的图像处理器。
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公开(公告)号：US12190243B2
公开(公告)日：2025-01-07
申请号：US18156704
申请日：2023-01-19
Inventor： Surinder Pal Singh , Giuseppe Desoli , Thomas Boesch
Abstract: An integrated circuit includes a reconfigurable stream switch and an arithmetic circuit. The stream switch, in operation, streams data. The arithmetic circuit has a plurality of inputs coupled to the reconfigurable stream switch. In operation, the arithmetic circuit generates an output according to AX+BY+C, where A, B and C are vector or scalar constants, and X and Y are data streams streamed to the arithmetic circuit through the reconfigurable stream switch.
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公开(公告)号：US12118451B2
公开(公告)日：2024-10-15
申请号：US15423272
申请日：2017-02-02
Inventor： Giuseppe Desoli , Thomas Boesch , Nitin Chawla , Surinder Pal Singh , Elio Guidetti , Fabio Giuseppe De Ambroggi , Tommaso Majo , Paolo Sergio Zambotti
IPC: G06N3/04 , G06F30/327 , G06F30/34 , G06F30/347 , G06N3/044 , G06N3/045 , G06N3/0464 , G06N3/047 , G06N3/084 , G06N20/00 , G06N20/10 , G06F9/445 , G06F13/40 , G06F15/78 , G06F115/02 , G06F115/08 , G06N3/063 , G06N3/08 , G06N7/01
CPC classification number: G06N3/0464 , G06F30/327 , G06F30/34 , G06F30/347 , G06N3/044 , G06N3/045 , G06N3/047 , G06N3/084 , G06N20/00 , G06N20/10 , G06F9/44505 , G06F13/4022 , G06F15/7817 , G06F2115/02 , G06F2115/08 , G06N3/04 , G06N3/063 , G06N3/08 , G06N7/01
Abstract: Embodiments are directed towards a system on chip (SoC) that implements a deep convolutional network heterogeneous architecture. The SoC includes a system bus, a plurality of addressable memory arrays coupled to the system bus, at least one applications processor core coupled to the system bus, and a configurable accelerator framework coupled to the system bus. The configurable accelerator framework is an image and deep convolutional neural network (DCNN) co-processing system. The SoC also includes a plurality of digital signal processors (DSPs) coupled to the system bus, wherein the plurality of DSPs coordinate functionality with the configurable accelerator framework to execute the DCNN.
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Patent Agency Ranking
公开(公告)号：US11836608B2
公开(公告)日：2023-12-05
申请号：US18056937
申请日：2022-11-18
Inventor： Thomas Boesch , Giuseppe Desoli , Surinder Pal Singh , Carmine Cappetta
CPC classification number: G06N3/063 , G06F9/5027 , H03M7/3082 , H03M7/6005
Abstract: Techniques and systems are provided for implementing a convolutional neural network. One or more convolution accelerators are provided that each include a feature line buffer memory, a kernel buffer memory, and a plurality of multiply-accumulate (MAC) circuits arranged to multiply and accumulate data. In a first operational mode the convolutional accelerator stores feature data in the feature line buffer memory and stores kernel data in the kernel data buffer memory. In a second mode of operation, the convolutional accelerator stores kernel decompression tables in the feature line buffer memory.
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公开(公告)号：US11360667B2
公开(公告)日：2022-06-14
申请号：US17012501
申请日：2020-09-04
Inventor： Nitin Chawla , Giuseppe Desoli , Anuj Grover , Thomas Boesch , Surinder Pal Singh , Manuj Ayodhyawasi
Abstract: A memory array arranged as a plurality of memory cells. The memory cells are configured to operate at a determined voltage. A memory management circuitry coupled to the plurality of memory cells tags a first set of the plurality of memory cells as low-voltage cells and tags a second set of the plurality of memory cells as high-voltage cells. A power source provides a low voltage to the first set of memory cells and provides a high voltage to the second set of memory cells based on the tags.
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公开(公告)号：US11977971B2
公开(公告)日：2024-05-07
申请号：US18167366
申请日：2023-02-10
Inventor： Surinder Pal Singh , Thomas Boesch , Giuseppe Desoli
IPC: G06T7/62 , G06F9/38 , G06F16/901 , G06F18/22 , G06N3/045 , G06N3/063 , G06N3/08 , G06T7/11 , G06T15/08 , G06V10/82 , G06V20/00 , G06V10/75
CPC classification number: G06N3/063 , G06F9/3877 , G06F16/9024 , G06F18/22 , G06N3/045 , G06N3/08 , G06T7/11 , G06T7/62 , G06T15/08 , G06V10/82 , G06V20/00 , G06V10/759
Abstract: A device include on-board memory, an applications processor, a digital signal processor (DSP) cluster, a configurable accelerator framework (CAF), and a communication bus architecture. The communication bus communicatively couples the applications processor, the DSP cluster, and the CAF to the on-board memory. The CAF includes a reconfigurable stream switch and data volume sculpting circuitry, which has an input and an output coupled to the reconfigurable stream switch. The data volume sculpting circuitry receives a series of frames, each frame formed as a two dimensional (2D) data structure, and determines a first dimension and a second dimension of each frame of the series of frames. Based on the first and second dimensions, the data volume sculpting circuitry determines for each frame a position and a size of a region-of-interest to be extracted from the respective frame, and extracts from each frame, data in the frame that is within the region-of-interest.
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公开(公告)号：US11880759B2
公开(公告)日：2024-01-23
申请号：US18172979
申请日：2023-02-22
Inventor： Giuseppe Desoli , Carmine Cappetta , Thomas Boesch , Surinder Pal Singh , Saumya Suneja
CPC classification number: G06N3/045 , G06F16/2282 , G06F18/217 , G06N3/04 , G06N3/063 , G06N3/08
Abstract: Embodiments of an electronic device include an integrated circuit, a reconfigurable stream switch formed in the integrated circuit along with a plurality of convolution accelerators and a decompression unit coupled to the reconfigurable stream switch. The decompression unit decompresses encoded kernel data in real time during operation of convolutional neural network.
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公开(公告)号：US11610362B2
公开(公告)日：2023-03-21
申请号：US17194055
申请日：2021-03-05
Inventor： Surinder Pal Singh , Thomas Boesch , Giuseppe Desoli
IPC: G06T7/62 , G06T7/11 , G06T15/08 , G06F16/901 , G06F9/38 , G06K9/62 , G06N3/08 , G06N3/04 , G06N3/063 , G06V20/00 , G06V10/82 , G06V10/75
Abstract: A device include on-board memory, an applications processor, a digital signal processor (DSP) cluster, a configurable accelerator framework (CAF), and at least one communication bus architecture. The communication bus communicatively couples the applications processor, the DSP cluster, and the CAF to the on-board memory. The CAF includes a reconfigurable stream switch and data volume sculpting circuitry, which has an input and an output coupled to the reconfigurable stream switch. The data volume sculpting circuitry receives a series of frames, each frame formed as a two dimensional (2D) data structure, and determines a first dimension and a second dimension of each frame of the series of frames. Based on the first and second dimensions, the data volume sculpting circuitry determines for each frame a position and a size of a region-of-interest to be extracted from the respective frame, and extracts from each frame, data in the frame that is within the region-of-interest.
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