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公开(公告)号：US20150235686A1
公开(公告)日：2015-08-20
申请号：US14183225
申请日：2014-02-18
发明人： Marco Pasotti , Abhishek Lal , Rajat Kulshrestha
摘要： According to various embodiments described herein, a circuit includes a decode logic circuit, a buffer coupled to the decode logic, a positive level shifter with an input coupled to receive address signals and an output coupled to the buffer, and a negative level shifter with an input coupled to receive the address signals and an output coupled to the buffer.
摘要翻译： 根据本文描述的各种实施例，电路包括解码逻辑电路，耦合到解码逻辑的缓冲器，具有耦合以接收地址信号的输入和耦合到缓冲器的输出的正电平移位器，以及负电平移位器，具有 输入耦合以接收地址信号和耦合到缓冲器的输出。
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公开(公告)号：US20170178722A1
公开(公告)日：2017-06-22
申请号：US15422290
申请日：2017-02-01
IPC分类号： G11C13/00
CPC分类号： G11C13/004 , G11C7/065 , G11C7/08 , G11C13/0004 , G11C13/0026 , G11C13/0028 , G11C13/0061 , G11C13/0097 , G11C2013/0042 , G11C2207/002
摘要： A memory device includes an array of phase-change memory (PCM) cells and complementary PCM cells. A column decoder is coupled to the array of PCM cells and complementary PCM cells, and a sense amplifier is coupled to the column decoder. The sense amplifier includes a current integrator configured to receive first and second currents of a given PCM cell and complementary PCM cell, respectively. A current-to-voltage converter is coupled to the current integrator and is configured to receive the first and second currents, and to provide first and second voltages of the given PCM cell and complementary PCM cell to first and second nodes, respectively. A logic circuit is coupled to the first and second nodes and is configured to disable the column decoder and to discharge the bitline and complementary bitline voltages in response to the first and second voltages.
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公开(公告)号：US20160099033A1
公开(公告)日：2016-04-07
申请号：US14506865
申请日：2014-10-06
发明人： Abhishek Lal , Vikas Rana , Marco Pasotti
摘要： A memory includes a column decoder performing at least two levels of decoding using a first level decoder that decodes between the column bit lines and first level decode lines and a second level decoder that decodes between the first level decode lines and second level decode lines. The second level decoder includes first transistors coupled between the first level decode lines and read output lines and second transistors coupled between the first level decode lines and write input lines. The first transistors have a first voltage rating and are driven by decode control signals referenced to a low supply voltage compatible with the first voltage rating. The second transistors have a second voltage rating, higher than the first voltage rating, and are driven by decode control signals referenced to a high supply voltage (in excess of the low supply voltage) compatible with the second voltage rating.
摘要翻译： 存储器包括列解码器，其使用在列位线和第一电平解码线之间解码的第一电平解码器和在第一电平解码线和第二电平解码线之间解码的第二电平解码器来执行解码的至少两个级别。 第二电平解码器包括耦合在第一电平解码线和读出输出线之间的第一晶体管和耦合在第一电平解码线和写输入线之间的第二晶体管。 第一晶体管具有第一电压额定值，并且由与第一额定电压兼容的低电源电压参考的解码控制信号驱动。 第二晶体管具有高于第一电压额定值的第二电压额定值，并且由与第二额定电压兼容的高电源电压（超过低电源电压）的解码控制信号驱动。
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公开(公告)号：US11615820B1
公开(公告)日：2023-03-28
申请号：US17490976
申请日：2021-09-30
发明人： Laura Capecchi , Marcella Carissimi , Marco Pasotti , Vikas Rana , Vivek Tyagi
摘要： A system and method for operating a memory cell is provided. A non-volatile memory storage device includes an array of memory cells of differential or single-ended type. In an embodiment, a regulator is coupled to a sense amplifier. The regulator is configured to generate a voltage to gate terminals of one or two transistors of the sense amplifier. In the differential type, the voltage is generated such that the first bias current and the second bias current have a current value equal to the sum of a maximum current flowing in a memory cell being in a RESET state and a fixed current. In the single-ended type, the regulated voltage is generated such that the first bias current and the second bias current have a current value equal to the sum of a fixed current and the reference current generated by the reference current source across temperature.
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公开(公告)号：US11424676B2
公开(公告)日：2022-08-23
申请号：US17145107
申请日：2021-01-08
发明人： Vikas Rana , Marco Pasotti , Fabio De Santis
摘要： A voltage supply circuit and a method for controlling a voltage supply circuit are provided. The voltage supply circuit includes a positive charge pump stage that generates a positive voltage and a negative charge pump stage that generates a negative voltage. The voltage supply circuit also includes a control stage that compares a voltage representative of the negative voltage with a reference voltage and causes a slope of the positive voltage to decrease when the voltage representative of the negative voltage exceeds the reference voltage.
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16.发明授权公开(公告)号：US11342031B2
公开(公告)日：2022-05-24
申请号：US17006510
申请日：2020-08-28
发明人： Marco Pasotti , Dario Livornesi , Roberto Bregoli , Vikas Rana , Abhishek Mittal
摘要： An integrated circuit includes a memory array and a read voltage regulator that generates read voltages from the memory array. The read voltage regulator includes a replica memory cell and the replica bitline current path. The replica memory cell is a replica of memory cells of the memory array. The replica bitline current path is a replica of current paths associated with deadlines of the memory array. The read voltage regulator generates a read voltage based on the current passed through the replica bitline current path. This read voltage is then supplied to the wordlines of the memory array during a read operation.
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公开(公告)号：US20210234460A1
公开(公告)日：2021-07-29
申请号：US17145107
申请日：2021-01-08
发明人： Vikas Rana , Marco Pasotti , Fabio De Santis
IPC分类号： H02M3/07
摘要： A voltage supply circuit and a method for controlling a voltage supply circuit are provided. The voltage supply circuit includes a positive charge pump stage that generates a positive voltage and a negative charge pump stage that generates a negative voltage. The voltage supply circuit also includes a control stage that compares a voltage representative of the negative voltage with a reference voltage and causes a slope of the positive voltage to decrease when the voltage representative of the negative voltage exceeds the reference voltage.
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公开(公告)号：US10068643B2
公开(公告)日：2018-09-04
申请号：US15422290
申请日：2017-02-01
摘要： A memory device includes an array of phase-change memory (PCM) cells and complementary PCM cells. A column decoder is coupled to the array of PCM cells and complementary PCM cells, and a sense amplifier is coupled to the column decoder. The sense amplifier includes a current integrator configured to receive first and second currents of a given PCM cell and complementary PCM cell, respectively. A current-to-voltage converter is coupled to the current integrator and is configured to receive the first and second currents, and to provide first and second voltages of the given PCM cell and complementary PCM cell to first and second nodes, respectively. A logic circuit is coupled to the first and second nodes and is configured to disable the column decoder and to discharge the bitline and complementary bitline voltages in response to the first and second voltages.
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公开(公告)号：US10049736B2
公开(公告)日：2018-08-14
申请号：US15433795
申请日：2017-02-15
发明人： Marco Pasotti , Marcella Carissimi , Vikas Rana
摘要： An integrated circuit includes an array of phase-change memory (PCM) cells, and bitlines coupled to the array of PCM cells. The integrated circuit also includes a first decoder circuit having a respective plurality of transistors having a first conductivity type being coupled together and to a given bitline from among the plurality thereof and configured to inject a program current pulse into a selected PCM cell. In addition, the integrated circuit includes a second decoder circuit having a plurality of transistors having a second conductivity type being coupled together and to the given bitline and configured to discharge the given bitline at an end of the program current pulse.
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公开(公告)号：US09634562B1
公开(公告)日：2017-04-25
申请号：US15177830
申请日：2016-06-09
发明人： Vikas Rana , Marco Pasotti , Fabio De Santis
CPC分类号： H02M3/073
摘要： A voltage doubler circuit supports operation in a positive voltage boosting mode to positively boost voltage from a first node to a second node and operation in a negative voltage boosting mode to negatively boost voltage from the second node to the first node. The voltage doubler circuits receive two clock signals having different high voltage levels. A series of voltage doubler circuit are connected in a charge pump with controllable operation in the first and second modes. A connecting circuit interconnects the first and second nodes of the voltage doubler circuits to provide a first connection path, with a first input voltage, to support the positive voltage boosting mode operation and a second connection path, with a proper input voltage, to support the negative voltage boosting mode. A discharge circuit is provided to discharge the voltage doubler circuits when operation of the charge pump circuit is terminated.
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