公开(公告)号：US20210399089A1

公开(公告)日：2021-12-23

申请号：US17346771

申请日：2021-06-14

Applicant: STMicroelectronics S.r.l.

Inventor： Mario Giuseppe SAGGIO ,  Angelo MAGRI' ,  Edoardo ZANETTI ,  Alfio GUARNERA

IPC: H01L29/06 ,  H01L29/16

Abstract: An electronic device includes a semiconductor body of silicon carbide, and a body region at a first surface of the semiconductor body. A source region is disposed in the body region. A drain region is disposed at a second surface of the semiconductor body. A doped region extends seamlessly at the entire first surface of the semiconductor body and includes one or more first sub-regions having a first doping concentration and one or more second sub-regions having a second doping concentration lower than the first doping concentration. Thus, the device has zones alternated to each other having different conduction threshold voltage and different saturation current.

公开(公告)号：US20210249268A1

公开(公告)日：2021-08-12

申请号：US17244393

申请日：2021-04-29

Applicant: STMICROELECTRONICS S.r.l.

Inventor： Edoardo ZANETTI ,  Simone RASCUNA' ,  Mario Giuseppe SAGGIO ,  Alfio GUARNERA ,  Leonardo FRAGAPANE ,  Cristina TRINGALI

IPC: H01L21/04 ,  H01L21/285 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H01L29/16 ,  H01L29/872

Abstract: A manufacturing method of an electronic device includes: forming a drift layer of an N type; forming a trench in the drift layer; forming an edge-termination structure alongside the trench by implanting dopant species of a P type; and forming a depression region between the trench and the edge-termination structure by digging the drift layer. The steps of forming the depression region and the trench are carried out at the same time. The step of forming the depression region comprises patterning the drift layer to form a structural connection with the edge-termination structure having a first slope, and the step of forming the trench comprises etching the drift layer to define side walls of the trench, which have a second slope steeper than the first slope.

公开(公告)号：US20250038060A1

公开(公告)日：2025-01-30

申请号：US18917464

申请日：2024-10-16

Applicant: STMicroelectronics S.r.l.

Inventor： Simone RASCUNA' ,  Claudio CHIBBARO ,  Alfio GUARNERA ,  Mario Giuseppe SAGGIO ,  Francesco LIZIO

IPC: H01L23/31 ,  H01L21/04 ,  H01L21/56 ,  H01L29/16

Abstract: An electronic power device includes a substrate of silicon carbide (SiC) having a front surface and a rear surface which lie in a horizontal plane and are opposite to one another along a vertical axis. The substrate includes an active area, provided in which are a number of doped regions, and an edge area, which is not active, distinct from and surrounding the active area. A dielectric region is arranged above the front surface, in at least the edge area. A passivation layer is arranged above the front surface of the substrate, and is in contact with the dielectric region in the edge area. The passivation layer includes at least one anchorage region that extends through the thickness of the dielectric region at the edge area, such as to define a mechanical anchorage for the passivation layer.

公开(公告)号：US20240014286A1

公开(公告)日：2024-01-11

申请号：US18345767

申请日：2023-06-30

Applicant: STMICROELECTRONICS S.r.l.

Inventor： Mario Giuseppe SAGGIO ,  Cateno Marco CAMALLERI ,  Alfio GUARNERA

IPC: H01L29/49 ,  H01L29/16 ,  H01L29/78 ,  H01L21/04 ,  H01L29/66

CPC classification number: H01L29/4933 ,  H01L29/1608 ,  H01L29/7802 ,  H01L21/049 ,  H01L29/66068

Abstract: A power MOSFET device includes a semiconductor body having a first main surface. The semiconductor body includes an active area facing the first main surface. The power MOSFET device includes an isolated-gate structure, which extends over the active area and includes a gate-oxide layer, which is made of insulating material and extends over the first main surface, and a gate region buried in the gate-oxide layer so as to be electrically insulated from the semiconductor body. The gate region includes a gate layer of polysilicon and at least one first silicide electrical-modulation region and one second silicide electrical-modulation region, which extend in the gate layer so as to face a top surface of the gate layer and to be arranged alongside one another and spaced apart from one another in a first plane.

公开(公告)号：US20230134850A1

公开(公告)日：2023-05-04

申请号：US18045784

申请日：2022-10-11

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Salvatore CASCINO ,  Alfio GUARNERA ,  Mario Giuseppe SAGGIO

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/66 ,  H01L21/04

Abstract: A semiconductor power device has a maximum nominal voltage and includes: a first conduction terminal and a second conduction terminal; a semiconductor body, containing silicon carbide and having a first conductivity type; body wells having a second conductivity type, housed in the semiconductor body and separated from one another by a body distance; source regions housed in the body wells; and floating pockets having the second conductivity type, formed in the semiconductor body at a distance from the body wells between a first face and a second face of the semiconductor body. The floating pockets are shaped and arranged relative to the body wells so that a maximum intensity of electrical field around the floating pockets is greater than a maximum intensity of electrical field around the body wells at least for values of a conduction voltage between the first conduction terminal and the second conduction terminal greater than a threshold voltage, the threshold voltage being less than the maximum nominal voltage.

公开(公告)号：US20230092543A1

公开(公告)日：2023-03-23

申请号：US18052510

申请日：2022-11-03

Applicant: STMICROELECTRONICS S.r.l.

Inventor： Simone RASCUNA' ,  Claudio CHIBBARO ,  Alfio GUARNERA ,  Mario Giuseppe SAGGIO ,  Francesco LIZIO

IPC: H01L23/31 ,  H01L21/04 ,  H01L21/56 ,  H01L29/16

Abstract: An electronic power device includes a substrate of silicon carbide (SiC) having a front surface and a rear surface which lie in a horizontal plane and are opposite to one another along a vertical axis. The substrate includes an active area, provided in which are a number of doped regions, and an edge area, which is not active, distinct from and surrounding the active area. A dielectric region is arranged above the front surface, in at least the edge area. A passivation layer is arranged above the front surface of the substrate, and is in contact with the dielectric region in the edge area. The passivation layer includes at least one anchorage region that extends through the thickness of the dielectric region at the edge area, such as to define a mechanical anchorage for the passivation layer.

公开(公告)号：US20220246723A1

公开(公告)日：2022-08-04

申请号：US17579474

申请日：2022-01-19

Applicant: STMicroelectronics S.r.l.

Inventor： Mario Giuseppe SAGGIO ,  Alessia Maria FRAZZETTO ,  Edoardo ZANETTI ,  Alfio GUARNERA

IPC: H01L29/08 ,  H01L29/16 ,  H01L29/10 ,  H01L29/78 ,  H01L21/04 ,  H01L29/66

Abstract: A vertical conduction MOSFET device includes a body of silicon carbide having a first conductivity type and a face. A metallization region extends on the face of the body. A body region of a second conductivity type extends in the body, from the face of the body, along a first direction parallel to the face and along a second direction transverse to the face. A source region of the first conductivity type extends towards the inside of the body region, from the face of the body. The source region has a first portion and a second portion. The first portion has a first doping level and extends in direct electrical contact with the metallization region. The second portion has a second doping level and extends in direct electrical contact with the first portion of the source region. The second doping level is lower than the first doping level.

公开(公告)号：US20210104445A1

公开(公告)日：2021-04-08

申请号：US17039289

申请日：2020-09-30

Applicant: STMicroelectronics S.r.l.

Inventor： Simone RASCUNA' ,  Claudio CHIBBARO ,  Alfio GUARNERA ,  Mario Giuseppe SAGGIO ,  Francesco LIZIO

IPC: H01L23/31 ,  H01L29/16 ,  H01L21/04 ,  H01L21/56

Abstract: An electronic power device includes a substrate of silicon carbide (SiC) having a front surface and a rear surface which lie in a horizontal plane and are opposite to one another along a vertical axis. The substrate includes an active area, provided in which are a number of doped regions, and an edge area, which is not active, distinct from and surrounding the active area. A dielectric region is arranged above the front surface, in at least the edge area. A passivation layer is arranged above the front surface of the substrate, and is in contact with the dielectric region in the edge area. The passivation layer includes at least one anchorage region that extends through the thickness of the dielectric region at the edge area, such as to define a mechanical anchorage for the passivation layer.

公开(公告)号：US20190172715A1

公开(公告)日：2019-06-06

申请号：US16209680

申请日：2018-12-04

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Edoardo ZANETTI ,  Simone RASCUNÁ ,  Mario Giuseppe SAGGIO ,  Alfio GUARNERA ,  Leonardo FRAGAPANE ,  Cristina TRINGALI

IPC: H01L21/04 ,  H01L21/285 ,  H01L29/66 ,  H01L29/16 ,  H01L29/872

Abstract: A manufacturing method of an electronic device includes: forming a drift layer of an N type; forming a trench in the drift layer; forming an edge-termination structure alongside the trench by implanting dopant species of a P type; and forming a depression region between the trench and the edge-termination structure by digging the drift layer. The steps of forming the depression region and the trench are carried out at the same time. The step of forming the depression region comprises patterning the drift layer to form a structural connection with the edge-termination structure having a first slope, and the step of forming the trench comprises etching the drift layer to define side walls of the trench, which have a second slope steeper than the first slope.