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    INTEGRATED MOS TRANSISTOR WITH SELECTIVE DISABLING OF CELLS THEREOF
    11.
    发明申请
    INTEGRATED MOS TRANSISTOR WITH SELECTIVE DISABLING OF CELLS THEREOF 有权

    公开(公告)号：US20220038094A1

    公开(公告)日：2022-02-03

    申请号：US17388920

    申请日：2021-07-29

    Applicant: STMicroelectronics S.r.l.

    Inventor： Davide Giuseppe PATTI

    IPC: H03K17/30 ,  H01L29/06 ,  H01L29/78 ,  H01L27/06 ,  H01L29/66

    Abstract: An integrated device includes at least one MOS transistor having a plurality of cells. In each of one or more of the cells a disabling structure is provided. The disabling structure is configured to be in a non-conductive condition when the MOS transistor is switched on in response to a control voltage comprised between a threshold voltage of the MOS transistor and an intervention voltage of the disabling structure, or to be in a conductive condition otherwise. A system comprising at least one integrated device as above is also proposed. Moreover, a corresponding process for manufacturing this integrated device is proposed.

    HIGH ELECTRON MOBILITY TRANSISTOR (HEMT) DEVICES AND METHODS
    12.
    发明申请
    HIGH ELECTRON MOBILITY TRANSISTOR (HEMT) DEVICES AND METHODS 有权

    公开(公告)号：US20210091219A1

    公开(公告)日：2021-03-25

    申请号：US17027118

    申请日：2020-09-21

    Applicant: STMicroelectronics S.r.l.

    Inventor： Davide Giuseppe PATTI

    IPC: H01L29/778 ,  H01L29/66 ,  H01L29/04 ,  H01L29/423

    Abstract: Embodiments are directed to high electron mobility transistor (HEMT) devices and methods. One such HEMT device includes a substrate having a first surface, and first and second heterostructures on the substrate and facing each other. Each of the first and second heterostructures includes a first semiconductor layer on the first surface of the substrate, a second semiconductor layer on the first surface of the substrate, and a two-dimensional electrode gas (2DEG) layer between the first and second semiconductor layers. A doped semiconductor layer is disposed between the first and second heterostructures, and a source contact is disposed on the first heterostructure and the second heterostructure.

    TRENCH-GATE FIELD EFFECT TRANSISTOR WITH IMPROVED ELECTRICAL PERFORMANCES AND CORRESPONDING MANUFACTURING PROCESS
    13.
    发明申请
    TRENCH-GATE FIELD EFFECT TRANSISTOR WITH IMPROVED ELECTRICAL PERFORMANCES AND CORRESPONDING MANUFACTURING PROCESS 审中-公开

    公开(公告)号：US20200027980A1

    公开(公告)日：2020-01-23

    申请号：US16518883

    申请日：2019-07-22

    Applicant: STMICROELECTRONICS S.R.L.

    Inventor： Salvatore PRIVITERA ,  Davide Giuseppe PATTI

    IPC: H01L29/78 ,  H01L29/66

    Abstract: A field effect transistor has a semiconductor layer with a top surface extending in a horizontal plane, and an active area defined in which are trench gate regions, which extend in depth with respect to the top surface and have an insulating coating layer and a conductive inner layer, and source regions, adjacent to the trench gate regions so as to form a conductive channel extending vertically. The trench gate regions have a plurality of first gate regions, which extend in length in the form of stripes through the active area along a first direction of the horizontal plane, and moreover a plurality of second gate regions, which extend in length in the form of stripes through the same active area along a second direction of the horizontal plane, orthogonal to, and crossing, the first gate regions. In particular, the first gate regions and second gate regions cross in the active area, joining with a non-zero curvature radius.

    INTEGRATED VACUUM MICROELECTRONIC STRUCTURE AND MANUFACTURING METHOD THEREOF
    15.
    发明申请
    INTEGRATED VACUUM MICROELECTRONIC STRUCTURE AND MANUFACTURING METHOD THEREOF 审中-公开
    集成真空微电子结构及其制造方法

    公开(公告)号：US20170032921A1

    公开(公告)日：2017-02-02

    申请号：US15291962

    申请日：2016-10-12

    Applicant: STMICROELECTRONICS S.R.L.

    Inventor： Davide Giuseppe PATTI ,  Gianleonardo GRASSO

    IPC: H01J9/02 ,  H01J21/10 ,  H01J1/304

    CPC classification number: H01J9/025 ,  G01K7/01 ,  H01J1/3044 ,  H01J21/10 ,  H01J21/105 ,  H01L29/12 ,  H01L29/66969 ,  H01L29/7827

    Abstract: An integrated vacuum microelectronic structure is described as having a highly doped semiconductor substrate, a first insulating layer placed above said doped semiconductor substrate, a first conductive layer placed above said first insulating layer, a second insulating layer placed above said first conductive layer, a vacuum trench formed within said first and second insulating layers and extending to the highly doped semiconductor substrate, a second conductive layer placed above said vacuum trench and acting as a cathode, a third metal layer placed under said highly doped semiconductor substrate and acting as an anode, said second conductive layer is placed adjacent to the upper edge of said vacuum trench, the first conductive layer is separated from said vacuum trench by portions of said second insulating layer and is in electrical contact with said second conductive layer.

    Abstract translation: 集成的真空微电子结构被描述为具有高度掺杂的半导体衬底，放置在所述掺杂半导体衬底之上的第一绝缘层，放置在所述第一绝缘层之上的第一导电层，放置在所述第一导电层上方的第二绝缘层，真空 形成在所述第一和第二绝缘层内并延伸到高掺杂半导体衬底的第二导电层，置于所述真空沟槽之上并用作阴极的第二导电层，置于所述高掺杂半导体衬底之下并用作阳极的第三金属层， 所述第二导电层邻近所述真空沟槽的上边缘放置，所述第一导电层通过所述第二绝缘层的一部分与所述真空沟槽分离，并与所述第二导电层电接触。

    TRENCH-GATE FIELD EFFECT TRANSISTOR WITH IMPROVED ELECTRICAL PERFORMANCES AND CORRESPONDING MANUFACTURING PROCESS
    16.
    发明公开
    TRENCH-GATE FIELD EFFECT TRANSISTOR WITH IMPROVED ELECTRICAL PERFORMANCES AND CORRESPONDING MANUFACTURING PROCESS 审中-公开

    公开(公告)号：US20230352578A1

    公开(公告)日：2023-11-02

    申请号：US18348990

    申请日：2023-07-07

    Applicant: STMICROELECTRONICS S.r.l.

    Inventor： Salvatore PRIVITERA ,  Davide Giuseppe PATTI

    IPC: H01L29/78 ,  H01L29/66

    CPC classification number: H01L29/7813 ,  H01L29/66734

    Abstract: A field effect transistor has a semiconductor layer with a top surface extending in a horizontal plane, and an active area defined in which are trench gate regions, which extend in depth with respect to the top surface and have an insulating coating layer and a conductive inner layer, and source regions, adjacent to the trench gate regions so as to form a conductive channel extending vertically. The trench gate regions have a plurality of first gate regions, which extend in length in the form of stripes through the active area along a first direction of the horizontal plane, and moreover a plurality of second gate regions, which extend in length in the form of stripes through the same active area along a second direction of the horizontal plane, orthogonal to, and crossing, the first gate regions. In particular, the first gate regions and second gate regions cross in the active area, joining with a non-zero curvature radius.

    TRENCH-GATE FIELD EFFECT TRANSISTOR WITH IMPROVED ELECTRICAL PERFORMANCES AND CORRESPONDING MANUFACTURING PROCESS
    17.
    发明申请
    TRENCH-GATE FIELD EFFECT TRANSISTOR WITH IMPROVED ELECTRICAL PERFORMANCES AND CORRESPONDING MANUFACTURING PROCESS 有权

    公开(公告)号：US20220352368A1

    公开(公告)日：2022-11-03

    申请号：US17867491

    申请日：2022-07-18

    Applicant: STMICROELECTRONICS S.R.L.

    Inventor： Salvatore PRIVITERA ,  Davide Giuseppe PATTI

    IPC: H01L29/78 ,  H01L29/66

    Abstract: A field effect transistor has a semiconductor layer with a top surface extending in a horizontal plane, and an active area defined in which are trench gate regions, which extend in depth with respect to the top surface and have an insulating coating layer and a conductive inner layer, and source regions, adjacent to the trench gate regions so as to form a conductive channel extending vertically. The trench gate regions have a plurality of first gate regions, which extend in length in the form of stripes through the active area along a first direction of the horizontal plane, and moreover a plurality of second gate regions, which extend in length in the form of stripes through the same active area along a second direction of the horizontal plane, orthogonal to, and crossing, the first gate regions. In particular, the first gate regions and second gate regions cross in the active area, joining with a non-zero curvature radius.

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