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    VERTICAL-GATE MOS TRANSISTOR WITH FIELD-PLATE ACCESS
    3.
    发明申请
    VERTICAL-GATE MOS TRANSISTOR WITH FIELD-PLATE ACCESS 审中-公开
    具有现场板访问的垂直栅极MOS晶体管

    公开(公告)号：US20140008722A1

    公开(公告)日：2014-01-09

    申请号：US13927600

    申请日：2013-06-26

    Applicant: STMicroelectronics S.r.l.

    Inventor： Simone Dario MARIANI ,  Daniele MERLINI ,  Fabrizio Fausto Renzo TOIA

    IPC: H01L29/78 ,  H01L29/66

    CPC classification number: H01L29/7827 ,  H01L29/407 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/66666 ,  H01L29/66734 ,  H01L29/7813

    Abstract: An embodiment of a vertical-gate transistor disposed on a die includes a first substrate portion of a first conductivity and a second substrate portion of a second conductivity. The die includes front and rear surfaces, the first portion extending from the front surface and the second portion extending from the rear surface to the first portion, at least one drain region of the second conductivity extending from the rear surface, and at least one cell. Each cell includes a source region of the second conductivity extending from the front surface, a conductive gate region extending from the front surface to a gate depth, a conductive field-plate region extending from the front surface to a field depth, a gate-insulating layer that insulates the gate region, and a plate-insulating layer that insulates the field-plate region. An intermediate insulating layer insulates the gate region from the field-plate region.

    Abstract translation: 设置在管芯上的垂直栅极晶体管的实施例包括具有第一导电性的第一衬底部分和具有第二导电性的第二衬底部分。 模具包括前表面和后表面，第一部分从前表面延伸，第二部分从后表面延伸到第一部分，从后表面延伸的至少一个第二导电漏极区域和至少一个电池单元 。 每个单元包括从前表面延伸的第二导电的源极区域，从前表面延伸到栅极深度的导电栅极区域，从前表面延伸到场深度的导电场板区域，栅极绝缘 使栅极区域绝缘的层，以及使场板区域绝缘的板绝缘层。 中间绝缘层使栅极区域与场板区域绝缘。

    PROCESS FOR MANUFACTURING INTEGRATED ELECTRONIC DEVICES, IN PARTICULAR CMOS DEVICES USING A BORDERLESS CONTACT TECHNIQUE
    6.
    发明申请
    PROCESS FOR MANUFACTURING INTEGRATED ELECTRONIC DEVICES, IN PARTICULAR CMOS DEVICES USING A BORDERLESS CONTACT TECHNIQUE 审中-公开
    使用无边界接触技术制造集成电子器件的特殊CMOS器件的工艺

    公开(公告)号：US20160351495A1

    公开(公告)日：2016-12-01

    申请号：US14966435

    申请日：2015-12-11

    Applicant: STMICROELECTRONICS S.R.L.

    Inventor： Sara PAOLILLO ,  Giovanni TAGLIABUE ,  Simone Dario MARIANI

    IPC: H01L23/522 ,  H01L27/092 ,  H01L21/8238 ,  H01L21/768 ,  H01L23/532

    CPC classification number: H01L23/5226 ,  H01L21/76802 ,  H01L21/76816 ,  H01L21/76819 ,  H01L21/76829 ,  H01L21/76877 ,  H01L21/823871 ,  H01L23/485 ,  H01L23/53295 ,  H01L27/092

    Abstract: For manufacturing an integrated electronic device, a protection layer, of a first material, is formed over a body having a non-planar surface; a first dielectric layer, of a second material, is formed over the protection layer, the second material being selectively etchable with respect to the first material; an intermediate layer, of a third material, is formed over the first dielectric layer, the third material being selectively etchable with respect to the second material; a second dielectric layer, of a fourth material, is formed over the intermediate layer, the fourth material being selectively etchable with respect to the third material; vias are formed through the second dielectric layer, the intermediate layer, the first dielectric layer, and the protection layer; and electrical contacts, of conductive material, are formed in the vias.

    Abstract translation: 为了制造集成电子器件，在具有非平面表面的主体上形成第一材料的保护层; 第二材料的第一介电层形成在保护层上方，第二材料相对于第一材料可选择性地蚀刻; 第三材料的中间层形成在第一介电层上，第三材料相对于第二材料可选择性地蚀刻; 第四材料的第二介电层形成在所述中间层上，所述第四材料相对于所述第三材料可选择性地蚀刻; 通过第二介电层，中间层，第一介电层和保护层形成通孔; 并且导电材料的电触点形成在通孔中。

    INTEGRATED DEVICE WITH DEEP PLUG UNDER SHALLOW TRENCH
    8.
    发明申请
    INTEGRATED DEVICE WITH DEEP PLUG UNDER SHALLOW TRENCH 有权

    公开(公告)号：US20210193658A1

    公开(公告)日：2021-06-24

    申请号：US17124671

    申请日：2020-12-17

    Applicant: STMicroelectronics S.r.l.

    Inventor： Andrea PALEARI ,  Simone Dario MARIANI ,  Irene BALDI ,  Daniela BRAZZELLI ,  Alessandra Piera MERLINI

    IPC: H01L27/092 ,  H01L21/762

    Abstract: An integrated device includes a deep plug. The deep plug is formed by a deep trench extending in a semiconductor body from a shallow surface of a shallow trench isolation. A trench contact makes contact with a conductive filler of the deep trench through the shallow trench at its shallow surface. A system includes at least one integrated device with the deep plug. Moreover, a corresponding process for manufacturing this integrated device includes steps for forming and filling the deep trench before forming the shallow trench isolation and trench window through which the trench contact extends to make contact with the conductive filler. The semiconductor body has a thickness, and the deep trench extends into the semiconductor body less than the thickness.

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