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    HIGH-VOLTAGE CAPACITOR, SYSTEM INCLUDING THE CAPACITOR AND METHOD FOR MANUFACTURING THE CAPACITOR
    1.
    发明申请
    HIGH-VOLTAGE CAPACITOR, SYSTEM INCLUDING THE CAPACITOR AND METHOD FOR MANUFACTURING THE CAPACITOR 有权

    公开(公告)号：US20210159309A1

    公开(公告)日：2021-05-27

    申请号：US17170550

    申请日：2021-02-08

    Applicant: STMICROELECTRONICS S.R.L.

    Inventor： Davide Giuseppe PATTI ,  Giuseppina VALVO ,  DelfoNunziato SANFILIPPO

    IPC: H01L49/02 ,  H01L23/522

    Abstract: In various embodiments, the present disclosure provides capacitors and methods of forming capacitors. In one embodiment, a capacitor includes a substrate, a first electrode on the substrate, a second electrode, and a first dielectric layer. A portion of the first electrode is exposed in a contact region. The first dielectric layer includes a first dielectric region between the first electrode and the second electrode, and a second dielectric region between the first dielectric region and the contact region. The second dielectric region is contiguous to the first dielectric region, and a surface of the second dielectric region defines a surface path between the first electrode and the contact region. The second dielectric region has a plurality of grooves that increase a spatial extension of said surface path.

    HIGH-VOLTAGE CAPACITOR, SYSTEM INCLUDING THE CAPACITOR AND METHOD FOR MANUFACTURING THE CAPACITOR
    7.
    发明申请
    HIGH-VOLTAGE CAPACITOR, SYSTEM INCLUDING THE CAPACITOR AND METHOD FOR MANUFACTURING THE CAPACITOR 审中-公开

    公开(公告)号：US20190096984A1

    公开(公告)日：2019-03-28

    申请号：US16144168

    申请日：2018-09-27

    Applicant: STMICROELECTRONICS S.R.L.

    Inventor： Davide Giuseppe PATTI ,  Giuseppina VALVO ,  DelfoNunziato SANFILIPPO

    IPC: H01L49/02 ,  H01L23/522

    Abstract: In various embodiments, the present disclosure provides capacitors and methods of forming capacitors. In one embodiment, a capacitor includes a substrate, a first electrode on the substrate, a second electrode, and a first dielectric layer. A portion of the first electrode is exposed in a contact region. The first dielectric layer includes a first dielectric region between the first electrode and the second electrode, and a second dielectric region between the first dielectric region and the contact region. The second dielectric region is contiguous to the first dielectric region, and a surface of the second dielectric region defines a surface path between the first electrode and the contact region. The second dielectric region has a plurality of grooves that increase a spatial extension of said surface path.

    INTEGRATED VACUUM MICROELECTRONIC STRUCTURE AND MANUFACTURING METHOD THEREOF
    8.
    发明申请
    INTEGRATED VACUUM MICROELECTRONIC STRUCTURE AND MANUFACTURING METHOD THEREOF 有权
    集成真空微电子结构及其制造方法

    公开(公告)号：US20150279988A1

    公开(公告)日：2015-10-01

    申请号：US14667215

    申请日：2015-03-24

    Applicant: STMICROELECTRONICS S.R.L.

    Inventor： Davide Giuseppe PATTI ,  Gianleonardo GRASSO

    IPC: H01L29/78 ,  H01L29/66 ,  H01L29/12

    CPC classification number: H01J9/025 ,  G01K7/01 ,  H01J1/3044 ,  H01J21/10 ,  H01J21/105 ,  H01L29/12 ,  H01L29/66969 ,  H01L29/7827

    Abstract: An integrated vacuum microelectronic structure is described as having a highly doped semiconductor substrate, a first insulating layer placed above said doped semiconductor substrate, a first conductive layer placed above said first insulating layer, a second insulating layer placed above said first conductive layer, a vacuum trench formed within said first and second insulating layers and extending to the highly doped semiconductor substrate, a second conductive layer placed above said vacuum trench and acting as a cathode, a third metal layer placed under said highly doped semiconductor substrate and acting as an anode, said second conductive layer is placed adjacent to the upper edge of said vacuum trench, the first conductive layer is separated from said vacuum trench by portions of said second insulating layer and is in electrical contact with said second conductive layer.

    Abstract translation: 集成的真空微电子结构被描述为具有高度掺杂的半导体衬底，放置在所述掺杂半导体衬底之上的第一绝缘层，放置在所述第一绝缘层之上的第一导电层，放置在所述第一导电层上方的第二绝缘层，真空 形成在所述第一和第二绝缘层内并延伸到高掺杂半导体衬底的第二导电层，置于所述真空沟槽之上并用作阴极的第二导电层，置于所述高掺杂半导体衬底之下并用作阳极的第三金属层， 所述第二导电层邻近所述真空沟槽的上边缘放置，所述第一导电层通过所述第二绝缘层的一部分与所述真空沟槽分离，并与所述第二导电层电接触。

    IGBT DEVICE WITH BURIED EMITTER REGIONS
    9.
    发明申请
    IGBT DEVICE WITH BURIED EMITTER REGIONS 审中-公开
    具有发射极区域的IGBT器件

    公开(公告)号：US20150048414A1

    公开(公告)日：2015-02-19

    申请号：US14496937

    申请日：2014-09-25

    Applicant: STMICROELECTRONICS S.r.l.

    Inventor： Davide Giuseppe PATTI

    IPC: H01L29/739 ,  H01L29/10 ,  H01L29/66 ,  H01L29/08

    CPC classification number: H01L29/7395 ,  H01L29/0804 ,  H01L29/0834 ,  H01L29/1095 ,  H01L29/66333

    Abstract: An embodiment of an IGBT device is integrated in a chip of semiconductor material including a substrate of a first type of conductivity, an active layer of a second type of conductivity formed on an inner surface of the substrate, a body region of the first type of conductivity extending within the active layer from a front surface thereof opposite the inner surface, a source region of the second type of conductivity extending within the body region from the front surface, a channel region being defined within the body region between the source region and the active layer, a gate element insulated from the front surface extending over the channel region, a collector terminal contacting the substrate on a rear surface thereof opposite the inner surface, an emitter terminal contacting the source region and the body region on the front surface, and a gate terminal contacting the gate element.

    Abstract translation: IGBT器件的实施例集成在半导体材料的芯片中，该半导体材料的芯片包括第一导电类型的衬底，形成在衬底的内表面上的第二类导电性的有源层，第一类型的主体区域 在活性层内从与内表面相反的前表面延伸的导电性，第二类型的导电源的源区从前表面延伸到体区内，沟道区被限定在源区与源区之间 活性层，与在沟道区域上延伸的前表面绝缘的栅极元件，在与内表面相反的后表面上接触衬底的集电极端子，与源极区域和前表面上的体区域接触的发射极端子，以及 栅极端子接触栅极元件。

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