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    On-SOI integrated circuit comprising a subjacent protection transistor
    12.
    发明授权
    On-SOI integrated circuit comprising a subjacent protection transistor 有权
    SOI-SOI集成电路，包括一个下层保护晶体管

    公开(公告)号：US09337302B2

    公开(公告)日：2016-05-10

    申请号：US13933379

    申请日：2013-07-02

    Applicant: Commissariat à l'énergie atomique et aux énergies alternatives ,  STMicroelectronics SA

    Inventor： Claire Fenouillet-Beranger ,  Pascal Fonteneau

    IPC: H01L29/66 ,  H01L27/02 ,  H01L27/12 ,  H01L27/06

    CPC classification number: H01L29/66477 ,  H01L27/0296 ,  H01L27/0688 ,  H01L27/1207

    Abstract: An integrated circuit features a FET, an UTBOX layer plumb with the FET, an underlayer ground plane with first doping plumb with the FET's gate and channel, first and second underlayer semiconducting elements, both plumb with the drain or source, electrodes in contact respectively with the ground plane and with the first element, one having first doping and being connected to a first voltage, the other having the first doping and connected to a second bias voltage different from the first, a semiconducting well having the second doping and plumb with the first ground plane and both elements, a first trench isolating the first FET from other components of the integrated circuit and extending through the layer into the well, and second and third trenches isolating the FET from the electrodes, and extending to a depth less than a plane/well interface.

    Abstract translation: 集成电路具有FET，具有FET的UTBOX层铅垂，具有FET的栅极和沟道的第一掺杂铅垂的下层接地层，第一和第二下层半导体元件，两者均与漏极或源极接触，电极分别接触 接地平面和第一元件，一个具有第一掺杂并且连接到第一电压，另一个具有第一掺杂并且连接到不同于第一掺杂的第二偏置电压，具有第二掺杂和铅垂的半导体阱与 第一接地平面和两个元件，第一沟槽将第一FET与集成电路的其它部件隔离并延伸穿过该阱进入阱，第二和第三沟槽将FET与电极隔离，并延伸至小于 平面/井界面。

    ON-SOI integrated circuit comprising a thyristor (SCR) for protection against electrostatic discharges
    13.
    发明授权
    ON-SOI integrated circuit comprising a thyristor (SCR) for protection against electrostatic discharges 有权
    ON-SOI集成电路包括用于防止静电放电的晶闸管（SCR）

    公开(公告)号：US09165943B2

    公开(公告)日：2015-10-20

    申请号：US13932371

    申请日：2013-07-01

    Applicant: Commissariat à l'énergie atomique et aux énergies alternatives ,  STMicroelectronics SA

    Inventor： Claire Fenouillet-Beranger ,  Pascal Fonteneau

    IPC: H01L27/12 ,  H01L27/02 ,  H01L27/06

    CPC classification number: H01L27/1203 ,  H01L27/0262 ,  H01L27/0296 ,  H01L27/0688 ,  H01L27/1207

    Abstract: An integrated circuit includes an UTBOX insulating layer under and plumb with first and second electronic components, and corresponding ground planes and oppositely-doped wells made plumb with them. The wells contact with corresponding ground planes. A pair of oppositely doped bias electrodes, suitable for connecting corresponding bias voltages, contacts respective wells and ground planes. A third electrode contacts the first well. A first trench isolates one bias electrode from the third electrode and extends through the layer and into the first well. A second trench isolates the first bias electrode from one component. This trench has an extent that falls short of reaching an interface between the first ground plane and the first well.

    Abstract translation: 集成电路包括在第一和第二电子部件下面并且铅垂的UTBOX绝缘层，以及相应的接地平面和与其相反的相对掺杂的阱。 油井与相应的地面接触。 一对相对掺杂的偏置电极适于连接相应的偏置电压，接触相应的阱和接地层。 第三电极接触第一阱。 第一沟槽将一个偏置电极与第三电极隔离并延伸穿过该层并进入第一阱。 第二沟槽将第一偏置电极与一个部件隔离。 该沟槽的程度不足以达到第一接地层与第一井之间的界面。

    Integrated circuit on SOI comprising a bipolar transistor with isolating trenches of distinct depths
    19.
    发明授权
    Integrated circuit on SOI comprising a bipolar transistor with isolating trenches of distinct depths 有权
    SOI上的集成电路包括具有不同深度的隔离沟槽的双极晶体管

    公开(公告)号：US09029955B2

    公开(公告)日：2015-05-12

    申请号：US13933396

    申请日：2013-07-02

    Applicant: Commissariat à l'énergie atomique et aux énergies alternatives ,  STMicroelectronics SA

    Inventor： Claire Fenouillet-Beranger ,  Pascal Fonteneau

    IPC: H01L29/66 ,  H01L27/02 ,  H01L27/06 ,  H01L29/786 ,  H01L27/12 ,  H01L29/732 ,  H01L29/06

    CPC classification number: H01L29/66234 ,  H01L27/0259 ,  H01L27/0296 ,  H01L27/0688 ,  H01L27/1207 ,  H01L29/0649 ,  H01L29/66272 ,  H01L29/732 ,  H01L29/78606

    Abstract: An integrated circuit includes a semiconductor substrate, a silicon layer, a buried isolating layer arranged between the substrate and the layer, a bipolar transistor comprising a collector and emitter having a first doping, and a base and a base contact having a second doping, the base forming a junction with the collector and emitter, the collector, emitter, base contact, and the base being coplanar, a well having the second doping and plumb with the collector, emitter, base contact and base, the well separating the collector, emitter and base contact from the substrate, having the second doping and extending between the base contact and base, a isolating trench plumb with the base and extending beyond the layer but without reaching a bottom of the emitter and collector, and another isolating trench arranged between the base contact, collector, and emitter, the trench extending beyond the buried layer into the well.

    Abstract translation: 集成电路包括半导体衬底，硅层，布置在衬底和层之间的掩埋隔离层，包括具有第一掺杂的集电极和发射极的双极晶体管，以及具有第二掺杂的基极和基极触点， 基极与集电极和发射极，集电极，发射极，基极接触和基极共面形成结，阱具有第二掺杂和铅与集电极，发射极，基极接触和基极，阱分离集电极，发射极 和基底接触，具有第二掺杂并且在基底接触和基底之间延伸;隔离沟槽铅与基底并延伸超出该层但不到达发射极和集电极的底部;以及另一隔离沟槽， 基极接触，集电极和发射极，沟槽延伸超过掩埋层进入阱。

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