公开(公告)号：US09018729B2

公开(公告)日：2015-04-28

申请号：US13895715

申请日：2013-05-16

Applicant: STMicroelectronics SA ,  STMicroelectronics (Crolles 2) SAS

Inventor： Raul Andres Bianchi ,  Pascal Fonteneau

IPC: H01L23/58 ,  H01L31/0256 ,  H01L27/144 ,  H01L31/18 ,  H01L29/66 ,  H01L29/866 ,  H01L29/06

CPC classification number: H01L31/0256 ,  H01L27/144 ,  H01L29/0684 ,  H01L29/66113 ,  H01L29/866 ,  H01L31/1892

Abstract: An avalance diode including, between two heavily-doped regions of opposite conductivity types arranged at the surface of a semiconductor region, a lightly-doped region, with length L of the lightly-doped region between the heavily-doped regions approximately ranging between 50 and 200 nm.

Abstract translation: 一种平均二极管，包括布置在半导体区域的表面处的相反导电类型的两个重掺杂区域之间的轻掺杂区域，重掺杂区域之间的轻掺杂区域的长度L大约在50和 200nm。

公开(公告)号：US10833094B2

公开(公告)日：2020-11-10

申请号：US15954874

申请日：2018-04-17

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Fausto Piazza ,  Sebastien Lagrasta ,  Raul Andres Bianchi ,  Simon Jeannot

IPC: H01L27/11546 ,  H01L21/28 ,  H01L27/06 ,  H01L49/02 ,  H01L21/02 ,  H01L21/3205 ,  H01L21/3213 ,  H01L27/11521 ,  H01L29/49 ,  H01L29/66 ,  H01L21/8234 ,  H01L27/11541

Abstract: An integrated circuit includes a high-voltage MOS (HV) transistor and a capacitor supported by a semiconductor substrate. A gate stack of the HV transistor includes a first insulating layer over the semiconductor layer and a gate electrode formed from a first polysilicon. The capacitor includes a first electrode made of the first polysilicon and a second electrode made of a second polysilicon and at least partly resting over the first electrode. A first polysilicon layer deposited over the semiconductor substrate is patterned to form the first polysilicon of the gate electrode and first electrode, respectively. A second polysilicon layer deposited over the semiconductor substrate is patterned to form the second polysilicon of the second electrode. Silicon oxide spacers laterally border the second electrode and the gate stack of the HV transistor. Silicon nitride spacers border the silicon oxide spacers.

公开(公告)号：US10833027B2

公开(公告)日：2020-11-10

申请号：US15784883

申请日：2017-10-16

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics (Rousset) SAS

Inventor： Mathieu Lisart ,  Raul Andres Bianchi ,  Benoit Froment

IPC: G01L23/00 ,  H01L23/00 ,  H04L9/32 ,  H04L9/00 ,  G06F9/4401 ,  H01L21/265 ,  H01L21/266 ,  H01L21/3205 ,  H01L21/8234 ,  H01L23/528 ,  H01L27/088 ,  H03K17/14

Abstract: An integrated device for physically unclonable functions is based on a set of MOS transistors exhibiting a random distribution of threshold voltages which are obtained by lateral implantations of dopants exhibiting non-predictable characteristics, resulting from implantations through a polysilicon layer. A certain number of these transistors form a group of gauge transistors which makes it possible to define a mean gate source voltage making it possible to bias the gates of certain others of these transistors (which are used to define the various bits of the unique code generated by the function). All these transistors consequently exhibit a random distribution of drain-source currents and a comparison of each drain-source current of a transistor associated with a bit of the digital code with a reference current corresponding to the average of this distribution makes it possible to define the logical value 0 or 1 of this bit.

公开(公告)号：US10217503B2

公开(公告)日：2019-02-26

申请号：US16151388

申请日：2018-10-04

Applicant: STMicroelectronics S.r.l. ,  STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics (Rousset) SAS

Inventor： Antonino Conte ,  Enrico Castaldo ,  Raul Andres Bianchi ,  Francesco La Rosa

IPC: G11C11/24 ,  G04F10/10

Abstract: A reading circuit for a charge-retention circuit stage is provided with a storage capacitor coupled between a first biasing terminal and a floating node, and a discharge element coupled between the floating node and a reference terminal. The reading circuit further has an operational amplifier having a first input terminal that is coupled to the floating node and receives a reading voltage, a second input terminal receives a reference voltage, and an output terminal on which it supplies an output voltage, the value of which is a function of the comparison between the reading voltage and the reference voltage and indicative of a residual charge in the storage capacitor. A shifting stage shifts the value of the reading voltage of the floating node, before the comparison is made between the reading voltage and the reference voltage for supplying the output voltage.

公开(公告)号：US10127966B2

公开(公告)日：2018-11-13

申请号：US15389751

申请日：2016-12-23

Applicant: STMicroelectronics S.r.l. ,  STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics (Rousset) SAS

Inventor： Antonino Conte ,  Enrico Castaldo ,  Raul Andres Bianchi ,  Francesco La Rosa

IPC: G11C11/24 ,  G04F10/10

Abstract: A reading circuit for a charge-retention circuit stage is provided with a storage capacitor coupled between a first biasing terminal and a floating node, and a discharge element coupled between the floating node and a reference terminal. The reading circuit further has an operational amplifier having a first input terminal that is coupled to the floating node and receives a reading voltage, a second input terminal receives a reference voltage, and an output terminal on which it supplies an output voltage, the value of which is a function of the comparison between the reading voltage and the reference voltage and indicative of a residual charge in the storage capacitor. A shifting stage shifts the value of the reading voltage of the floating node, before the comparison is made between the reading voltage and the reference voltage for supplying the output voltage.

公开(公告)号：US20180061781A1

公开(公告)日：2018-03-01

申请号：US15638883

申请日：2017-06-30

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Sebastien Petitdidier ,  Nicolas Hotellier ,  Raul Andres Bianchi ,  Alexis Farcy ,  Benoît Froment

IPC: H01L23/00 ,  H01L23/522 ,  H01L23/528 ,  H01L23/31 ,  H01L23/29 ,  H01L21/311 ,  H01L21/768 ,  H03K3/3565

CPC classification number: H01L23/576 ,  H01L21/31111 ,  H01L21/76802 ,  H01L21/76831 ,  H01L21/76877 ,  H01L21/76898 ,  H01L23/291 ,  H01L23/293 ,  H01L23/3171 ,  H01L23/481 ,  H01L23/49855 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/57 ,  H01L23/573 ,  H01L23/585 ,  H01L23/642 ,  H03K3/3565

Abstract: A semiconductor chip includes at least two insulated vias passing through the chip from the front face to the rear face in which, on the side of the rear face, the vias are connected to one and the same conducting strip and, on the side of the front face, each via is separated from a conducting pad by a layer of a dielectric.

公开(公告)号：US20140342524A1

公开(公告)日：2014-11-20

申请号：US14447699

申请日：2014-07-31

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Grégory Bidal ,  Laurent Favennec ,  Raul Andres Bianchi

IPC: H01L21/762 ,  H01L21/28 ,  H01L29/66

CPC classification number: H01L21/76224 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/28202 ,  H01L21/76232 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66477 ,  H01L29/78

Abstract: An integrated circuit including at least one isolating trench that delimits an active area made of a monocrystalline semiconductor material, the or each trench comprising an upper portion including an insulating layer that encapsulates a lower portion of the trench, the lower portion being at least partly buried in the active area and the encapsulation layer comprising nitrogen or carbon.

Abstract translation: 一种集成电路，其包括限定由单晶半导体材料制成的有源区域的至少一个隔离沟槽，所述或每个沟槽包括上部，该上部包括封装沟槽的下部的绝缘层，所述下部至少部分地被埋置 在活性区域和包含氮或碳的包封层。

公开(公告)号：US11336853B2

公开(公告)日：2022-05-17

申请号：US17063192

申请日：2020-10-05

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics (Research & Development) Limited

Inventor： Raul Andres Bianchi ,  Matteo Maria Vignetti ,  Bruce Rae

IPC: H04N5/3745 ,  H04N5/378

Abstract: The present disclosure relates to a device that includes a photodiode having a first terminal that is coupled by a resistor to a first rail configured to receive a high supply potential and a second terminal that is coupled by a switch to a second rail configured to receive a reference potential. A read circuit is configured to provide a pulse when the photodiode enters into avalanche, and a control circuit is configured to control an opening of the switch in response to a beginning of the pulse and to control a closing of the switch in response to an end of the pulse.

公开(公告)号：US20190035450A1

公开(公告)日：2019-01-31

申请号：US16151388

申请日：2018-10-04

Applicant: STMicroelectronics S.r.l. ,  STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics (Rousset) SAS

Inventor： Antonino Conte ,  Enrico Castaldo ,  Raul Andres Bianchi ,  Francesco La Rosa

IPC: G11C11/24 ,  G04F10/10

Abstract: A reading circuit for a charge-retention circuit stage is provided with a storage capacitor coupled between a first biasing terminal and a floating node, and a discharge element coupled between the floating node and a reference terminal. The reading circuit further has an operational amplifier having a first input terminal that is coupled to the floating node and receives a reading voltage, a second input terminal receives a reference voltage, and an output terminal on which it supplies an output voltage, the value of which is a function of the comparison between the reading voltage and the reference voltage and indicative of a residual charge in the storage capacitor. A shifting stage shifts the value of the reading voltage of the floating node, before the comparison is made between the reading voltage and the reference voltage for supplying the output voltage.

公开(公告)号：US20180277496A1

公开(公告)日：2018-09-27

申请号：US15784883

申请日：2017-10-16

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics (Rousset) SAS

Inventor： Mathieu Lisart ,  Raul Andres Bianchi ,  Benoit Froment

IPC: H01L23/00 ,  H01L27/088 ,  H01L23/528 ,  H03K17/14 ,  H01L21/8234 ,  H01L21/265 ,  H01L21/266 ,  H01L21/3205 ,  G06F9/44

Abstract: An integrated device for physically unclonable functions is based on a set of MOS transistors exhibiting a random distribution of threshold voltages which are obtained by lateral implantations of dopants exhibiting non-predictable characteristics, resulting from implantations through a polysilicon layer. A certain number of these transistors form a group of gauge transistors which makes it possible to define a mean gate source voltage making it possible to bias the gates of certain others of these transistors (which are used to define the various bits of the unique code generated by the function). All these transistors consequently exhibit a random distribution of drain-source currents and a comparison of each drain-source current of a transistor associated with a bit of the digital code with a reference current corresponding to the average of this distribution makes it possible to define the logical value 0 or 1 of this bit.