公开(公告)号：US11205621B2

公开(公告)日：2021-12-21

申请号：US16808090

申请日：2020-03-03

Applicant: STMICROELECTRONICS, INC.

Inventor： John H. Zhang ,  Walter Kleemeier ,  Paul Ferreira ,  Ronald K. Sampson

IPC: H01L23/544 ,  H01L21/66 ,  H01L25/065 ,  H01L25/00

Abstract: A device is provided that includes a first die having a first alignment structure that includes a plurality of first transmission columns arranged in a pattern and a second die positioned on the first die, the second die having a second alignment structure that includes a plurality of second transmission columns arranged in the same pattern as the first transmission columns. The first and second transmission columns are each coplanar with a first surface and a second surface of the first and second die, respectively.

公开(公告)号：US09870999B2

公开(公告)日：2018-01-16

申请号：US14951050

申请日：2015-11-24

Applicant: STMicroelectronics, Inc.

Inventor： John H. Zhang ,  Walter Kleemeier ,  Paul Ferreira ,  Ronald K. Sampson

IPC: H01L23/544 ,  H01L21/66 ,  H01L25/065 ,  H01L25/00

CPC classification number: H01L23/544 ,  H01L22/14 ,  H01L22/22 ,  H01L22/34 ,  H01L25/0657 ,  H01L25/50 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2223/5446 ,  H01L2224/16 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06593 ,  H01L2924/1461 ,  H01L2924/00

Abstract: A device is provided that includes a first die having a first alignment structure that includes a plurality of first transmission columns arranged in a pattern and a second die positioned on the first die, the second die having a second alignment structure that includes a plurality of second transmission columns arranged in the same pattern as the first transmission columns. The first and second transmission columns are each coplanar with a first surface and a second surface of the first and second die, respectively.

公开(公告)号：US09543397B2

公开(公告)日：2017-01-10

申请号：US14931078

申请日：2015-11-03

Applicant: STMicroelectronics, Inc.

Inventor： Walter Kleemeier ,  John Hongguang Zhang

IPC: H01L21/00 ,  H01L29/417 ,  H01L29/786 ,  H01L27/12 ,  H01L21/84 ,  H01L29/49

CPC classification number: H01L29/41766 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/41733 ,  H01L29/4975 ,  H01L29/78603 ,  H01L29/78648

Abstract: An integrated circuit transistor is formed on and in a substrate. A trench in the substrate is at least partially filed with a metal material to form a source (or drain) contact buried in the substrate. The substrate further includes a source (or drain) region epitaxially grown above the source (or drain) contact. The substrate further includes a channel region adjacent to the source (or drain) region. A gate dielectric is provided on top of the channel region and a gate electrode is provided on top of the gate dielectric. The substrate is preferably of the silicon on insulator (SOI) type.

Abstract translation: 集成电路晶体管形成在衬底上和衬底中。 衬底中的沟槽至少部分地与金属材料填充以形成埋在衬底中的源极（或漏极）接触。 衬底还包括在源极（或漏极）触点上方外延生长的源极（或漏极）区域。 衬底还包括与源极（或漏极）区域相邻的沟道区域。 栅极电介质设置在沟道区域的顶部，栅电极设置在栅极电介质的顶部。 衬底优选为绝缘体上硅（SOI）型。

公开(公告)号：US09324660B2

公开(公告)日：2016-04-26

申请号：US14038574

申请日：2013-09-26

Applicant: STMicroelectronics, Inc.

Inventor： John H. Zhang ,  Walter Kleemeier ,  Paul Ferreira ,  Ronald K. Sampson

IPC: H01L23/544 ,  H01L21/66 ,  H01L25/065 ,  H01L25/00

CPC classification number: H01L23/544 ,  H01L22/14 ,  H01L22/22 ,  H01L22/34 ,  H01L25/0657 ,  H01L25/50 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2223/5446 ,  H01L2224/16 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06593 ,  H01L2924/1461 ,  H01L2924/00

Abstract: A device is provided that includes a first die having a first alignment structure that includes a plurality of first transmission columns arranged in a pattern and a second die positioned on the first die, the second die having a second alignment structure that includes a plurality of second transmission columns arranged in the same pattern as the first transmission columns. The first and second transmission columns are each coplanar with a first surface and a second surface of the first and second die, respectively.

公开(公告)号：US09646939B2

公开(公告)日：2017-05-09

申请号：US15090996

申请日：2016-04-05

Applicant: International Business Machines Corporation ,  STMicroelectronics, Inc.

Inventor： John H. Zhang ,  Lawrence A. Clevenger ,  Carl Radens ,  Yiheng Xu ,  Byoung Youp Kim ,  Walter Kleemeier

IPC: H01L21/4763 ,  H01L23/00 ,  H01L21/768 ,  H01L21/66 ,  H01L23/528 ,  H01L23/532 ,  H01L23/522

CPC classification number: H01L23/562 ,  H01L21/76805 ,  H01L21/76843 ,  H01L21/76897 ,  H01L22/12 ,  H01L22/14 ,  H01L22/32 ,  H01L23/5223 ,  H01L23/5226 ,  H01L23/5227 ,  H01L23/5228 ,  H01L23/528 ,  H01L23/53266 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Various embodiments facilitate die protection for an integrated circuit. In one embodiment, a multilayer structure is formed in multiple levels and along the edges of a die to prevent and detect damages to the die. The multilayer structure includes a support layer, a first plurality of dielectric pillars overlying the support layer, a metal layer that fills spaces between the first plurality of dielectric pillars, an insulation layer overlying the first plurality of dielectric pillars and the metal layer, a second plurality of dielectric pillars overlying the insulation layer, and a second metal layer that fills spaces between the second plurality of dielectric pillars.

公开(公告)号：US09337087B1

公开(公告)日：2016-05-10

申请号：US14586688

申请日：2014-12-30

Applicant: STMicroelectronics, Inc. ,  International Business Machines Corporation

Inventor： John H. Zhang ,  Lawrence A. Clevenger ,  Carl Radens ,  Yiheng Xu ,  Byoung Youp Kim ,  Walter Kleemeier

IPC: H01L21/4763 ,  H01L21/768 ,  H01L23/522

CPC classification number: H01L23/562 ,  H01L21/76805 ,  H01L21/76843 ,  H01L21/76897 ,  H01L22/12 ,  H01L22/14 ,  H01L22/32 ,  H01L23/5223 ,  H01L23/5226 ,  H01L23/5227 ,  H01L23/5228 ,  H01L23/528 ,  H01L23/53266 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Various embodiments facilitate die protection for an integrated circuit. In one embodiment, a multilayer structure is formed in multiple levels and along the edges of a die to prevent and detect damages to the die. The multilayer structure includes a support layer, a first plurality of dielectric pillars overlying the support layer, a metal layer that fills spaces between the first plurality of dielectric pillars, an insulation layer overlying the first plurality of dielectric pillars and the metal layer, a second plurality of dielectric pillars overlying the insulation layer, and a second metal layer that fills spaces between the second plurality of dielectric pillars.

Abstract translation: 各种实施例便于集成电路的管芯保护。 在一个实施例中，多层结构形成在多个层次上并沿着模具的边缘，以防止和检测对模具的损坏。 所述多层结构包括支撑层，覆盖所述支撑层的第一多个介电柱，填充所述第一多个介电柱之间的空间的金属层，覆盖所述第一多个介电柱和所述金属层的绝缘层，第二 覆盖绝缘层的多个介电柱，以及填充第二多个介电柱之间的空间的第二金属层。

公开(公告)号：US20160118305A1

公开(公告)日：2016-04-28

申请号：US14942504

申请日：2015-11-16

Applicant: STMicroelectronics, Inc.

Inventor： Walter Kleemeier ,  Qing Liu

IPC: H01L21/8238 ,  H01L29/78 ,  H01L21/84 ,  H01L21/02 ,  H01L29/66

CPC classification number: H01L21/823814 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02584 ,  H01L21/8238 ,  H01L21/823821 ,  H01L21/823871 ,  H01L21/84 ,  H01L27/092 ,  H01L27/0924 ,  H01L27/1203 ,  H01L27/1211 ,  H01L29/45 ,  H01L29/456 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/778 ,  H01L29/7789 ,  H01L29/7838

Abstract: An integrated circuit includes a substrate supporting a transistor having a source region and a drain region. A high dopant concentration delta-doped layer is present on the source region and drain region of the transistor. A set of contacts extend through a pre-metal dielectric layer covering the transistor. A silicide region is provided at a bottom of the set of contacts. The silicide region is formed by a salicidation reaction between a metal present at the bottom of the contact and the high dopant concentration delta-doped layer on the source region and drain region of the transistor.

Abstract translation: 集成电路包括支撑具有源极区和漏极区的晶体管的衬底。 晶体管的源极区和漏极区存在高掺杂浓度的δ掺杂层。 一组触点延伸穿过覆盖晶体管的预金属介电层。 硅化物区域设置在该组触点的底部。 硅化物区域由接触底部存在的金属与晶体管的源极区域和漏极区域上的高掺杂浓度δ-掺杂层之间的水化反应形成。

公开(公告)号：US20150357477A1

公开(公告)日：2015-12-10

申请号：US14298000

申请日：2014-06-06

Applicant: STMicroelectronics, Inc.

Inventor： John Hongguang Zhang ,  Walter Kleemeier

IPC: H01L29/786 ,  H01L27/12

CPC classification number: H01L29/41766 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/41733 ,  H01L29/4975 ,  H01L29/78603 ,  H01L29/78648

Abstract: An integrated circuit transistor is formed on and in a substrate. A trench in the substrate is at least partially filed with a metal material to form a source (or drain) contact buried in the substrate. The substrate further includes a source (or drain) region epitaxially grown above the source (or drain) contact. The substrate further includes a channel region adjacent to the source (or drain) region. A gate dielectric is provided on top of the channel region and a gate electrode is provided on top of the gate dielectric. The substrate is preferably of the silicon on insulator (SOI) type.

Abstract translation: 集成电路晶体管形成在衬底上和衬底中。 衬底中的沟槽至少部分地与金属材料填充以形成埋在衬底中的源极（或漏极）接触。 衬底还包括在源极（或漏极）触点上方外延生长的源极（或漏极）区域。 衬底还包括与源极（或漏极）区域相邻的沟道区域。 栅极电介质设置在沟道区域的顶部，栅电极设置在栅极电介质的顶部。 衬底优选为绝缘体上硅（SOI）型。