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11.发明授权公开(公告)号：US11775037B2
公开(公告)日：2023-10-03
申请号：US17540041
申请日：2021-12-01
发明人： Loic Pallardy , Michael Soulie
IPC分类号： G06F1/24 , G06F9/4401 , G06F13/40 , G06F11/14 , G06F15/78
CPC分类号： G06F1/24 , G06F9/4401 , G06F11/1441 , G06F13/4068 , G06F15/7807 , G06F2213/40
摘要： The method for resetting a master device, configured to initiate transactions on a bus of a system on a chip, includes monitoring a completed or not state of the transactions initiated by the master device. In the case of reception of a command to reset the master device, the method includes a transmission of an effective reset command to the master device when the transactions initiated by the master device are in the completed state.
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公开(公告)号：US11614949B2
公开(公告)日：2023-03-28
申请号：US16899327
申请日：2020-06-11
IPC分类号： G06F13/40 , G06F9/4401 , G06F9/30 , G06F9/345 , G06F9/445
摘要： An integrated circuit comprises a processing unit configured for booting up with a set of boot instructions, then for determining the size of the instructions of an application programme and potentially rebooting on its own initiative, while being reconfigured, in order for it to execute the instructions of the application program. Only one boot memory is needed as a consequence.
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公开(公告)号：US20230015027A1
公开(公告)日：2023-01-19
申请号：US17812883
申请日：2022-07-15
发明人： Michel Jaouen , Loic Pallardy
IPC分类号： G06F21/62 , G06F12/0802
摘要： In an embodiment a method for managing access rights of software tasks executed by a processing unit (CPU) using a cache memory containing execution data of the tasks in memory locations, each execution data having an attribute representative of a level of access right of the respective task, includes changing the attributes of the locations of the cache memory when the access rights of at least one task changes and retaining the execution data contained in the locations of the cache memory.
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14.发明申请公开(公告)号：US20220179659A1
公开(公告)日：2022-06-09
申请号：US17540041
申请日：2021-12-01
发明人： Loic Pallardy , Michael Soulie
IPC分类号： G06F9/4401 , G06F13/40
摘要： The method for resetting a master device, configured to initiate transactions on a bus of a system on a chip, includes monitoring a completed or not state of the transactions initiated by the master device. In the case of reception of a command to reset the master device, the method includes a transmission of an effective reset command to the master device when the transactions initiated by the master device are in the completed state.
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公开(公告)号：US20230161486A1
公开(公告)日：2023-05-25
申请号：US18058613
申请日：2022-11-23
发明人： Loic Pallardy , Michel Jaouen
IPC分类号： G06F3/06
CPC分类号： G06F3/0622 , G06F3/0637 , G06F3/0673
摘要： In accordance with an embodiment, a method for managing a memory within a system-on-a-chip including a processor, a memory and a firewall device, includes: generating, by the processor, a request to access the memory, where the request has a access permission level; controlling, by the firewall device, access to the at least one memory region of the memory as a function of the access permission level of the request and a respective access permission level associated with at least one memory region; and erasing, by the firewall device, the at least one memory regions when its respective access permission level is modified, where erasing comprises performing a hardware-implemented erasure.
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公开(公告)号：US20230161484A1
公开(公告)日：2023-05-25
申请号：US17989389
申请日：2022-11-17
发明人： Loic Pallardy , Michel Jaouen
IPC分类号： G06F3/06
CPC分类号： G06F3/0622 , G06F3/0655 , G06F3/0673
摘要： In embodiments, a system includes a first and a second processing unit, a memory, and a firewall device. The first processing unit operates in a secure mode and generates memory access requests having a secure level. The second processing unit operates in a non-secure mode and generates memory access requests having a non-secure level. The memory includes a first memory area that can be shared between the first and second processing units. The firewall device includes a first firewall circuit with a first configuration authorizing access to the first memory area in the presence of a secure or non-secure level access request. The firewall circuit includes a second configuration prohibiting access to the first memory area in the presence of a secure level access request and authorizing access to the first memory area only in the presence of a non-secure level access request.
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公开(公告)号：US20220156217A1
公开(公告)日：2022-05-19
申请号：US17587954
申请日：2022-01-28
发明人： Loic Pallardy , Nicolas Saux
IPC分类号： G06F13/40 , G06F13/362
摘要： A system including a first port configured to simultaneously couple with a first device and a second device; and a management circuit configured to route a data signal received from a first controller to the first device in response to receiving a first-device direction from the first controller and route the data signal received from the first controller to the second device in response to receiving a second-device direction from the first controller unless an override condition for the management circuit is satisfied.
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18.发明公开公开(公告)号：US20230342279A1
公开(公告)日：2023-10-26
申请号：US18306032
申请日：2023-04-24
发明人： Michel Jaouen , Loic Pallardy
CPC分类号： G06F11/3466 , G06F11/3612
摘要： A method is provided for monitoring an execution of a selected program code portion stored in a memory address range between a start address and an end address. The method includes starting a timing when a program counter points to the start address of the selected program code portion. Current values of the program counter are compared with a set of target addresses specific to the selected program code portion including the end address of the selected program code portion. The timing is stopped when the program counter points to the end address of the selected program code portion. An error signal is generated in response to the timing duration being outside a nominal duration range specific to the selected program code portion.
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19.发明公开公开(公告)号：US20230161863A1
公开(公告)日：2023-05-25
申请号：US18058130
申请日：2022-11-22
发明人： Michel Jaouen , Loic Pallardy , Ludovic Barre
IPC分类号： G06F21/44
CPC分类号： G06F21/44
摘要： In an embodiment a method includes compiling, by a processor in a compiling phase, a software program intended to be executed by the processor, the processor having secure and non-secure access right level execution contexts, and/or privileged and non-privileged access right level execution contexts and generating, in the compilation phase, instructions in machine language having an exclusively secure access right level when the instructions are intended to be executed in the secure access right level execution context, and instructions having a non-privileged access right level when the instructions are intended to be executed in the non-privileged access right level execution context.
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公开(公告)号：US20220164016A1
公开(公告)日：2022-05-26
申请号：US17517382
申请日：2021-11-02
发明人： Gerald Baeza , Pascal Paillet , Loic Pallardy
IPC分类号： G06F1/324 , G06F1/3206
摘要： In an embodiment a method for managing a low-power mode of an electronic device includes at a first request for transitioning an electronic device to a low-power mode, storing values of a first counter and a second counter of the electronic device on a first edge of a first clock and at a second request for transitioning the electronic device out of the low-power mode calculating a number of periods of a second clock between a second edge of the first clock and the first edge, the second edge being later than the first edge and updating the value of the second counter with a calculated value, wherein the first clock drives the first counter and the second clock drives the second counter, the second clock being faster than the first clock.
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