TIME TO DIGITAL CONVERTER
    14.
    发明公开

    公开(公告)号:US20240118397A1

    公开(公告)日:2024-04-11

    申请号:US18390534

    申请日:2023-12-20

    摘要: In an embodiment, a method includes: receiving a first plurality of digital codes from a TDC; generating a coarse histogram from the first plurality of digital codes; detecting a peak coarse bin from the plurality of coarse bins; after receiving the first plurality of digital codes, receiving a second plurality of digital codes from the TDC; and generating a fine histogram from the second plurality of digital codes based on the detected peak coarse bin, where a fine histogram depth range is narrower than a coarse histogram depth range, where a lower fine histogram depth is lower or equal to a lower coarse peak depth, and where a higher fine histogram depth is higher or equal to a higher coarse peak depth.

    Voltage controlled steered VCSEL driver

    公开(公告)号:US11728621B2

    公开(公告)日:2023-08-15

    申请号:US16891936

    申请日:2020-06-03

    发明人: John Kevin Moore

    IPC分类号: H01S5/042 H01S5/068 H01S5/42

    摘要: An electronic device includes laser emitters, and a laser driver generating a laser drive signal for the laser emitters based upon a feedback control signal. A steering circuit selectively steers the laser drive signal to a different selected one of the plurality of laser emitters and prevents the laser drive signal from being steered to non-selected ones of the plurality of laser emitters, during each of a plurality of time periods. Control circuitry senses a magnitude of a current of the laser drive signal and generates the feedback control signal based thereupon. The feedback control signal is generated so as to cause the laser driver to generate the laser drive signal as having a current with a substantially constant magnitude.

    Dynamic latch based SPAD front end
    17.
    发明授权

    公开(公告)号:US11525904B2

    公开(公告)日:2022-12-13

    申请号:US16661119

    申请日:2019-10-23

    摘要: A time-of-flight ranging system disclosed herein includes a receiver asserting a photon received signal in response to detection of light that has reflected off a target and returned to the time-of-flight ranging system. A first latch circuit has first and second data inputs receiving a first pair of differential timing references, the first latch circuit latching data values at its first and second data inputs to first and second data outputs based upon assertion of the photon received signal. A first counter counts latching events of the first latch circuit during which the first data output is asserted, and a second counter counts latching events of the first latch circuit during which the second data output is asserted. Processing circuitry determines distance to the target based upon counted latching events output from the first and second counters.

    ROUTING FOR DTOF SENSORS
    19.
    发明申请

    公开(公告)号:US20210382152A1

    公开(公告)日:2021-12-09

    申请号:US16895477

    申请日:2020-06-08

    IPC分类号: G01S7/4863 G01S17/89

    摘要: A ToF sensor includes an array of pixels having first and second subsets of pixels, first and second pluralities of TDCs, a routing bus having first and second pluralities of bus drivers, and a controller configured to: when the first subset of pixels is active and the second subset of pixels is not active, control the first plurality of bus drivers to route events from half of the pixels of the first subset to the first plurality of TDCs and control the first and second pluralities of bus drivers to route events from the other half of the pixels of the first subset to the second plurality of TDCs, and when the first subset of pixels is not active and the second subset of pixels is active, control the first plurality of bus drivers to route events from the second subset of pixels to the first plurality of TDCs.

    Single reference clock time to digital converter

    公开(公告)号:US10715754B2

    公开(公告)日:2020-07-14

    申请号:US15877551

    申请日:2018-01-23

    摘要: In an embodiment, a TDC includes: a clock input configured to receive a reference clock that is synchronized with a first event; a clock generation circuit configured to generate a first clock at a first output of the clock generation circuit based on the reference clock, the first clock having a second frequency lower than the reference clock; a data input configured to receive an input stream of pulses, where the input stream of pulses is based on the first event; a sampling circuit having an input register, the sampling circuit coupled to the data input, the sampling circuit configured to continuously sample the input stream of pulses into the input register based on the reference clock; and output terminals configured to stream time stamps based on the input stream of pulses at the second frequency, where the stream of time stamps is synchronized with the first clock.