公开(公告)号：US08928381B1

公开(公告)日：2015-01-06

申请号：US13940713

申请日：2013-07-12

Applicant: STMicroelectronics Asia Pacific Pte. Ltd.

Inventor： Beng-Heng Goh

IPC: H03K3/037 ,  H03K19/00

CPC classification number: H03K3/037 ,  G01R31/318541

Abstract: Configurable flip-flop cells for use in scan chain configurations include one or more multiplexers, a flip-flop, and one or more logic gates. The logic gates are configurable, through modification of different metallization or semiconductor layers, to operate as spare gates or to disable flip-flop cell outputs based selection signal switching between scan shift and capture mode. When disabling flip-flop cell outputs, the logic gates are configured to receive both a test signal and a data input signal and select one of the two to pass to the flip-flop based on the selection signal. When used as spare gates, the logic gates receive external inputs and provide spare gate outputs to circuitry on an integrated circuit that is external to the flip-flop cells.

Abstract translation: 用于扫描链配置的可配置触发器单元包括一个或多个多路复用器，触发器和一个或多个逻辑门。 逻辑门可通过不同金属化或半导体层的修改来配置，作为备用栅极运行，或禁止基于触发器单元输出的选择信号在扫描移位和捕捉模式之间切换。 当禁止触发器单元输出时，逻辑门被配置为接收测试信号和数据输入信号，并且基于选择信号选择两者之一传递到触发器。 当用作备用栅极时，逻辑门接收外部输入，并为触发器单元外部的集成电路上的电路提供备用栅极输出。

公开(公告)号：US20180226957A1

公开(公告)日：2018-08-09

申请号：US15425277

申请日：2017-02-06

Applicant: STMicroelectronics Asia Pacific Pte Ltd

Inventor： Beng-Heng Goh ,  Yi Ren Chin

IPC: H03K5/151 ,  G11C19/28 ,  H03K3/3562 ,  H03L7/00

CPC classification number: H03K5/1515 ,  G11C7/22 ,  G11C7/222 ,  G11C19/28 ,  G11C19/287 ,  H03L7/00

Abstract: Disclosed herein is an electronic device including a flip flop and clock generation circuitry for controlling the flip flop. The flip flop includes a master latch receiving input for the flip flop, with the master latch latching the received input to its output in response to a first clock. The slave latch receives input from the output of the master latch, and latches the received input to its output in response to a second clock. The clock generation circuitry is configured to logically combine a device clock and an input clock to produce the first and second clocks.

公开(公告)号：US09311977B2

公开(公告)日：2016-04-12

申请号：US14469860

申请日：2014-08-27

Applicant: STMicroelectronics Asia Pacific Pte Ltd

Inventor： Beng-Heng Goh

IPC: G11C8/00 ,  G11C8/06 ,  G11C8/04 ,  G11C8/10 ,  G11C8/18 ,  G11C7/10

CPC classification number: G11C8/06 ,  G11C7/10 ,  G11C8/04 ,  G11C8/10 ,  G11C8/18

Abstract: A waveform generator circuit includes a memory with address locations storing output waveform defining data bits. An address counter generates an address for sequentially addressing the address locations in the memory. The memory responds by sequentially outputting the output waveform defining data bits at the addressed locations. An output circuit receives the waveform defining data bits output from the memory and operates to generate an output signal waveform having logic state values dependent on the sequentially output waveform defining data bits.

Abstract translation: 波形发生器电路包括具有存储定义数据位的输出波形的地址位置的存储器。 地址计数器产生用于顺序寻址存储器中的地址位置的地址。 存储器通过在寻址的位置顺序地输出定义数据位的输出波形来进行响应。 输出电路接收定义从存储器输出的数据位的波形，并且操作以产生具有取决于定义数据位的顺序输出波形的逻辑状态值的输出信号波形。

公开(公告)号：US20160064055A1

公开(公告)日：2016-03-03

申请号：US14469860

申请日：2014-08-27

Applicant: STMicroelectronics Asia Pacific Pte Ltd

Inventor： Beng-Heng Goh

IPC: G11C8/06 ,  G11C8/10 ,  G11C8/18 ,  G11C8/04

CPC classification number: G11C8/06 ,  G11C7/10 ,  G11C8/04 ,  G11C8/10 ,  G11C8/18

Abstract: A waveform generator circuit includes a memory with address locations storing output waveform defining data bits. An address counter generates an address for sequentially addressing the address locations in the memory. The memory responds by sequentially outputting the output waveform defining data bits at the addressed locations. An output circuit receives the waveform defining data bits output from the memory and operates to generate an output signal waveform having logic state values dependent on the sequentially output waveform defining data bits.

Abstract translation: 波形发生器电路包括具有存储定义数据位的输出波形的地址位置的存储器。 地址计数器产生用于顺序寻址存储器中的地址位置的地址。 存储器通过在寻址的位置顺序地输出定义数据位的输出波形来进行响应。 输出电路接收定义从存储器输出的数据位的波形，并且操作以产生具有取决于定义数据位的顺序输出波形的逻辑状态值的输出信号波形。

公开(公告)号：US20150039956A1

公开(公告)日：2015-02-05

申请号：US13954227

申请日：2013-07-30

Applicant: STMicroelectronics Asia Pacific Pte. Ltd.

Inventor： Beng-Heng Goh

IPC: G01R31/3177

CPC classification number: G01R31/318541 ,  G01R31/318525

Abstract: A new flip-flop cell that is more efficient in scan chain configuration includes a multiplexer, storage element (e.g., a flip-flop), an inverter, and multiple logic gates. The flip-flop cell is configured to receive both a test signal and a data input signal and select one of the two to pass to the storage element based on a scan enable signal that indicates either a capture mode or a scan shift mode. In capture mode, the data input signal is passed to the storage element, and the internal outputs of the flip-flop are supplied to the logic gates. Based on the internal outputs and scan enable signal, the logic gates disable either one of two outputs of the flip-flop cell. In capture mode, a test flip-flop cell output is disabled. In scan shift mode, a standard function flip-flop cell output is disabled.

Abstract translation: 在扫描链配置中更有效的新触发器单元包括多路复用器，存储元件（例如，触发器），反相器和多个逻辑门。 触发器单元被配置为接收测试信号和数据输入信号，并且基于指示捕获模式或扫描移位模式的扫描使能信号，选择两者之一传递到存储元件。 在捕捉模式下，数据输入信号被传递到存储元件，并且触发器的内部输出被提供给逻辑门。 基于内部输出和扫描使能信号，逻辑门禁用触发器单元的两个输出中的任一个。 在捕捉模式下，禁用测试触发器单元输出。 在扫描移位模式下，禁用标准功能触发器单元输出。