公开(公告)号：US20180285225A1

公开(公告)日：2018-10-04

申请号：US15475277

申请日：2017-03-31

Applicant: STMicroelectronics International N.V.

Inventor： Tejinder Kumar ,  Rakesh Malik

IPC: G06F11/22 ,  G06F11/263 ,  G06F11/273

CPC classification number: G06F11/221 ,  G06F11/076 ,  G06F11/263 ,  G06F11/2733

Abstract: Disclosed herein is a test apparatus for a device under test. The test apparatus includes a voltage translator coupled to receive test data from the device under test, over a physical interface, using one of a plurality of I/O standards, with the voltage translator being capable of communication using each of the plurality of I/O standards. A programmable interface is configured to receive the test data from the voltage translator. A bit error rate determination circuit is configured to receive the test data from the programmable interface and to determine a bit error rate of reception of the test data over the physical interface based upon a comparison of the test data to check data.

公开(公告)号：US20180164370A1

公开(公告)日：2018-06-14

申请号：US15375542

申请日：2016-12-12

Applicant: STMicroelectronics International N.V.

Inventor： Tejinder Kumar ,  Suchi Prabhu Tandel ,  Rakesh Malik

IPC: G01R31/317 ,  G01R31/3193

CPC classification number: G01R31/31703 ,  G01R31/3171 ,  G01R31/31932 ,  G01R31/31935 ,  G11C15/00 ,  G11C29/36 ,  G11C29/38 ,  G11C29/44 ,  G11C2029/0405 ,  G11C2029/2602

Abstract: Disclosed herein is a test circuit for testing a device under test (DUT). The test circuit receives a test pattern output by the DUT. A content addressable memory (CAM) stores expected test data at a plurality of address locations, receives the test pattern, and outputs an address of the CAM containing expected test data matching the received test pattern. A memory also stores the expected test data at address locations corresponding to the address locations of the CAM. A control circuit causes the memory to output the expected test data stored therein at the address output by the CAM. Comparison circuitry receives the test pattern from the input, and compares that received test pattern to the expected test data output by the control circuit, and generates an error count as a function of a number of bit mismatches between the received test pattern and the expected test data.

公开(公告)号：US09300317B2

公开(公告)日：2016-03-29

申请号：US14930708

申请日：2015-11-03

Applicant: STMicroelectronics International N.V.

Inventor： Rakesh Malik ,  Chandrajit Debnath ,  Ashish Sharma Kumar ,  Pratap Narayan Singh

IPC: H03M1/34 ,  H03M1/12 ,  H03M1/06 ,  H03M1/46 ,  H03M1/00

CPC classification number: H03M1/125 ,  H03M1/00 ,  H03M1/0612 ,  H03M1/069 ,  H03M1/0695 ,  H03M1/12 ,  H03M1/46 ,  H03M1/462

Abstract: An asynchronous SAR ADC converts an analog signal into a series of digital pulses in an efficient, low power manner. In synchronous SAR ADC circuits, a separate and cumbersome clock signal is used to trigger the internal circuitry of the SAR ADC. Instead of triggering the components of the SAR DAC synchronously with a clock signal, the asynchronous solution uses its own internal signals to trigger its components in an asynchronous cyclic manner. Further, in order to increase efficiency and guard against circuit failures due to difficulties arising from transient signals, the asynchronous SAR ADC may also include a delay circuit for introducing a variable delay to the SAR ADC cycle.

Abstract translation: 异步SAR ADC以有效，低功耗的方式将模拟信号转换为一系列数字脉冲。 在同步SAR ADC电路中，单独和繁琐的时钟信号用于触发SAR ADC的内部电路。 异步解决方案不是以时钟信号同步触发SAR DAC的组件，而是以其自身的内部信号以异步循环方式触发其组件。 此外，为了提高效率并防止由于瞬态信号引起的困难而导致的电路故障，异步SAR ADC还可以包括用于将可变延迟引入SAR ADC周期的延迟电路。