公开(公告)号：US20060010408A1

公开(公告)日：2006-01-12

申请号：US10887599

申请日：2004-07-09

申请人： Stefan Auracher ,  Claus Pribbernow ,  Andreas Hils ,  Juergen Dirks ,  Manisha Patel ,  James Imper

发明人： Stefan Auracher ,  Claus Pribbernow ,  Andreas Hils ,  Juergen Dirks ,  Manisha Patel ,  James Imper

IPC分类号： G06F17/50 ,  G06F1/04

CPC分类号： G06F17/5077 ,  G06F1/10 ,  G06F2217/62

摘要： A method of placing a clock signal supply network in a design representation for an integrated circuit. The design representation may comprise a plurality of clockable circuit cells. The method may comprise identifying a first of the clockable circuit cells in the design representation. The method may further comprise identifying a second of the clockable circuit cells in the design representation. The second clockable circuit cell may have a clock timing dependent relation relative to the first clockable circuit cell. The method may further comprise configuring the clock signal supply network. The clock signal supply network may be configured to supply respective clock signals to the first and said second clockable circuit cells. The clock signal supply network may be configured to route the respective clock signals such that a timing difference between the respective clock signals is protected from process, voltage and temperature (PVT) influences.

公开(公告)号：US20110066905A1

公开(公告)日：2011-03-17

申请号：US12558611

申请日：2009-09-14

申请人： Stefan G. Block ,  Herbert Preuthen ,  Farid Labib ,  Stephan Habel ,  Claus Pribbernow

发明人： Stefan G. Block ,  Herbert Preuthen ,  Farid Labib ,  Stephan Habel ,  Claus Pribbernow

IPC分类号： G06F11/00

CPC分类号： G01R31/31701 ,  G01R31/318541

摘要： An improvement to an integrated circuit of a type having a test enable line for enabling an electrical test of the integrated circuit only when the test enable line is at a logical high value, and output lines that are only used during the electrical test of the integrated circuit, where the improvement is a switch circuit for disabling a state change in the output lines when the test enable line is at a logical low value. In this manner, the output lines do not switch during functional use of the integrated circuit, and cannot be aggressors on the data signals that are carried by the data lines that are used during the functional use of the integrated circuit. In addition, these non-switching output lines can act as guard traces that run between the data lines, further electrically isolating the data lines from one another. Further, because they do not switch during functional use of the integrated circuit, the overall power consumption of the integrated circuit is reduced.

摘要翻译： 对具有用于仅在测试使能线处于逻辑高值时才能进行集成电路的电气测试的测试使能线的类型的集成电路的改进以及仅在集成电路的电测试期间使用的输出线 电路，其中改进是当测试使能线处于逻辑低值时禁止输出线路中的状态改变的开关电路。 以这种方式，输出线在集成电路的功能使用期间不切换，并且不能成为在集成电路的功能使用期间由数据线承载的数据信号的侵略者。 此外，这些非开关输出线可以用作在数据线之间运行的保护迹线，进一步将数据线彼此电隔离。 此外，由于在集成电路的功能使用期间不切换，集成电路的总体功耗降低。

公开(公告)号：US07392344B2

公开(公告)日：2008-06-24

申请号：US11226086

申请日：2005-09-13

申请人： Claus Pribbernow ,  David Parker

发明人： Claus Pribbernow ,  David Parker

IPC分类号： G06F12/04

CPC分类号： G06F12/0802 ,  G06F2212/601

摘要： A data-processing system and method include a processor core associated with a cache controller. A plurality of cached memory components is associated with the processor core and the cache controller. A cached processor is provided, which supports a plurality of varying sizes of instruction and data cache, wherein the cached processor comprises a processor core separated from the cache controller and the plurality of cached memory components, thereby permitted the cached processor to support varying sizes of cache memory in a flexible memory arrangement thereof.

摘要翻译： 数据处理系统和方法包括与高速缓存控制器相关联的处理器核心。 多个缓存的存储器组件与处理器核心和高速缓存控制器相关联。 提供了缓存的处理器，其支持多个不同大小的指令和数据高速缓存，其中缓存的处理器包括与高速缓存控制器和多个高速缓存的存储器组件分离的处理器核，从而允许高速缓存的处理器支持不同大小的 缓存存储器在其灵活的存储器布置中。

公开(公告)号：US07032190B2

公开(公告)日：2006-04-18

申请号：US10724996

申请日：2003-12-01

申请人： Stefan Auracher ,  Claus Pribbernow ,  Andreas Hils

发明人： Stefan Auracher ,  Claus Pribbernow ,  Andreas Hils

IPC分类号： G06F17/50

CPC分类号： G06F17/5054 ,  G06F17/5068 ,  H01L27/0203 ,  H01L27/11803

摘要： A representation of a macro for an integrated circuit layout. The representation may define sub-circuit cells of a module. The module may have a predefined functionality. The sub-circuit cells may include at least one reusable circuit cell. The reusable circuit cell may be configured such that when the predefined functionality of the module is not used, the reusable circuit cell is available for re-use.

摘要翻译： 用于集成电路布局的宏的表示。 该表示可以定义模块的子电路单元。 模块可以具有预定义的功能。 子电路单元可以包括至少一个可重复使用的电路单元。 可重复使用的电路单元可以被配置为使得当不使用模块的预定义功能时，可重复使用的电路单元可用于重复使用。

公开(公告)号：US20050116738A1

公开(公告)日：2005-06-02

申请号：US10724949

申请日：2003-12-01

申请人： Stefan Auracher ,  Claus Pribbernow ,  Andreas Hils

发明人： Stefan Auracher ,  Claus Pribbernow ,  Andreas Hils

IPC分类号： G06F17/50 ,  H01L27/02 ,  H01L27/118 ,  H03K19/00

CPC分类号： G06F17/5054 ,  G06F17/5068 ,  G06F2217/64 ,  H01L27/0203 ,  H01L27/11803

摘要： An integrated circuit comprising a die having a surface. The die may comprise first and second areas. The first area may comprise first circuit cells. The first circuit cells may be configurable by user defined interconnections from above the surface. The second area may comprise a plurality of sub-circuit cells. The sub-circuit cells may form a module having a predefined functionality. The sub-circuit cells may include at least one second circuit cell. The second circuit cell may be configured such that when the predefined functionality of the module is not used, the second circuit cell is configurable by user defined interconnections from above the surface.

摘要翻译： 一种包括具有表面的模具的集成电路。 模具可以包括第一和第二区域。 第一区域可以包括第一电路单元。 第一电路单元可以由表面上方的用户定义的互连来配置。 第二区域可以包括多个子电路单元。 子电路单元可以形成具有预定义功能的模块。 子电路单元可以包括至少一个第二电路单元。 第二电路单元可以被配置为使得当不使用模块的预定义功能时，第二电路单元可以由来自表面上方的用户定义的互连来配置。

公开(公告)号：US08583844B2

公开(公告)日：2013-11-12

申请号：US13118603

申请日：2011-05-31

申请人： Sakthivel Komarasamy Pullagoundapatti ,  Srinivasa Rao Kothamasu ,  Venkat Rao Vallapaneni ,  Claus Pribbernow ,  Shrinivas Sureban

发明人： Sakthivel Komarasamy Pullagoundapatti ,  Srinivasa Rao Kothamasu ,  Venkat Rao Vallapaneni ,  Claus Pribbernow ,  Shrinivas Sureban

IPC分类号： G06F13/00 ,  G06F13/364

CPC分类号： G06F13/364 ,  G06F13/4022 ,  G06F15/17312 ,  G06F2213/0038

摘要： A system and method for optimizing slave transaction ID width based on sparse connection between multiple masters and multiple slaves in a multilayer multilevel interconnect system-on-chip (SOC) architecture are disclosed. In one embodiment, slave transaction ID widths are computed for a first processing subsystem and a second processing subsystem including multiple masters and multiple slaves. Further, a slave transaction ID for each master to any slave in the first processing subsystem and in the second processing subsystem is generated based on the computed slave transaction ID width. Furthermore, sparse connection information between the multiple masters and multiple slaves is determined via a first bus matrix in the first processing subsystem. A first optimized slave transaction ID for each master to any slave in the first processing subsystem is then generated by removing don't care bits in each generated slave transaction ID based on the sparse connection information.

摘要翻译： 公开了一种基于多层互连片上系统（SOC）架构中的多个主机与多个从机之间的稀疏连接来优化从事事务ID宽度的系统和方法。 在一个实施例中，为第一处理子系统和包括多个主器件和多个从器件的第二处理子系统计算从事事务ID宽度。 此外，基于所计算的从事事务ID宽度，生成针对第一处理子系统和第二处理子系统中的任何从属设备的每个主机的从事事务ID。 此外，多个主站和多个从站之间的稀疏连接信息通过第一处理子系统中的第一总线矩阵来确定。 然后，通过根据稀疏连接信息去除每个生成的从事事务ID中的无关位，来生成第一处理子系统中的每个主设备到每个主设备的第一优化的从事事务ID。

公开(公告)号：US20100153824A1

公开(公告)日：2010-06-17

申请号：US12335096

申请日：2008-12-15

申请人： Claus Pribbernow ,  Stephan Habel

发明人： Claus Pribbernow ,  Stephan Habel

IPC分类号： H03M13/05 ,  G06F11/07

CPC分类号： H03K3/0375 ,  G06F11/1008

摘要： In one embodiment, a circuit has multiple flip-flops with gated clock inputs controlled by an enable signal, where the clock signal is gated in order to reduce power consumption by the circuit. The circuit has an error detection and correction (EDC) module that is active when the enable signal is low in order to detect and correct soft errors of the flip-flops. The EDC module generates and stores an error-correction code based on the data outputs of the flip-flops. The EDC module then compares the stored error-correction code to a presently generated error-correction code, where if they are not identical, then the EDC (a) determines (i) that a soft error has occurred and (ii) which flip-flop suffered the soft error and (b) flips a corresponding error-correction signal to provide a correct corresponding output signal while the enable signal is low.

摘要翻译： 在一个实施例中，电路具有多个触发器，门控时钟输入由使能信号控制，其中时钟信号被选通以减少电路的功耗。 该电路具有错误检测和校正（EDC）模块，当使能信号为低电平时，该模块有效，以检测和纠正触发器的软错误。 EDC模块基于触发器的数据输出产生并存储纠错码。 然后，EDC模块将存储的纠错码与当前生成的纠错码进行比较，如果它们不相同，则EDC（a）确定（i）已发生软错误，以及（ii） 触发器出现软错误，（b）翻转相应的纠错信号，以在使能信号为低电平时提供正确的相应输出信号。

公开(公告)号：US20070101062A1

公开(公告)日：2007-05-03

申请号：US11266132

申请日：2005-11-02

申请人： Claus Pribbernow ,  David Parker

发明人： Claus Pribbernow ,  David Parker

IPC分类号： G06F12/00

CPC分类号： G06F12/0802 ,  G06F2212/601

摘要： A data-processing system and method are disclosed, which include a cached processor for processing data, and a plurality of memory components that communicate with the cached processor. The cached processor is separated from the memory components such that the cached processor provides support for the memory components, thereby providing a diffused memory architecture with diffused memory capabilities. The memory components can constitute, for example, memory devices such as diffused memory, matrix memory, R-Cell memory components, and the like, depending on design considerations.

摘要翻译： 公开了一种数据处理系统和方法，其包括用于处理数据的缓存处理器以及与缓存处理器通信的多个存储器组件。 缓存的处理器与存储器组件分离，使得缓存的处理器提供对存储器组件的支持，从而提供具有扩散存储器能力的扩散存储器架构。 取决于设计考虑，存储器组件可以构成例如诸如扩散存储器，矩阵存储器，R-Cell存储器组件等的存储器件。

公开(公告)号：US20070061517A1

公开(公告)日：2007-03-15

申请号：US11226086

申请日：2005-09-13

申请人： Claus Pribbernow ,  David Parker

发明人： Claus Pribbernow ,  David Parker

IPC分类号： G06F12/00

CPC分类号： G06F12/0802 ,  G06F2212/601

摘要： A data-processing system and method include a processor core associated with a cache controller. A plurality of cached memory components is associated with the processor core and the cache controller. A cached processor is provided, which supports a plurality of varying sizes of instruction and data cache, wherein the cached processor comprises a processor core separated from the cache controller and the plurality of cached memory components, thereby permitted the cached processor to support varying sizes of cache memory in a flexible memory arrangement thereof.

摘要翻译： 数据处理系统和方法包括与高速缓存控制器相关联的处理器核心。 多个缓存的存储器组件与处理器核心和高速缓存控制器相关联。 提供了缓存的处理器，其支持多个不同大小的指令和数据高速缓存，其中缓存的处理器包括与高速缓存控制器和多个高速缓存的存储器组件分离的处理器核，从而允许高速缓存的处理器支持不同大小的 缓存存储器在其灵活的存储器布置中。

公开(公告)号：US20070011642A1

公开(公告)日：2007-01-11

申请号：US11176514

申请日：2005-07-07

申请人： Claus Pribbernow

发明人： Claus Pribbernow

IPC分类号： G06F17/50

CPC分类号： G06F17/5045

摘要： An application specific configurable logic IP module includes (1) a system level configuration controller; (2) at least one standardized interconnect communicatively coupled to the system level configuration controller; (3) at least one standardized configuration port for programming the application specific configurable logic IP module; (4) an embedded programmable logic fabric, communicatively coupled to the system level configuration controller and the at least one standardized interconnect, for mapping arithmetic functions into standard cells; (5) at least one scalable configurable logic module; and (6) a programmable routing matrix. The system level configuration controller is suitable for selecting a standard for the at least one standardized interconnect, the at least one standardized configuration port, and a number of embedded programmable logic functions, and for controlling the programmable routing matrix.

摘要翻译： 应用专用可配置逻辑IP模块包括（1）系统级配置控制器; （2）至少一个通信地耦合到所述系统级配置控制器的标准化互连; （3）至少一个用于对应用特定的可配置逻辑IP模块进行编程的标准化配置端口; （4）嵌入式可编程逻辑结构，通信地耦合到所述系统级配置控制器和所述至少一个标准化互连，用于将算术功能映射到标准单元中; （5）至少一个可扩展可配置逻辑模块; 和（6）可编程路由矩阵。 系统级配置控制器适用于选择用于至少一个标准化互连，至少一个标准化配置端口和多个嵌入式可编程逻辑功能的标准，并用于控制可编程路由矩阵。