公开(公告)号：US09136284B2

公开(公告)日：2015-09-15

申请号：US13915070

申请日：2013-06-11

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Sung Kyun Park ,  Jeong Min Park ,  Jung-Soo Lee ,  Jin Ho Ju

IPC: H01L27/12 ,  H01L27/15

CPC classification number: H01L27/124 ,  H01L27/1222 ,  H01L27/1248 ,  H01L27/1259

Abstract: A thin film transistor array panel according to an exemplary embodiment of the present invention includes: an insulation substrate; a thin film transistor disposed on the insulation substrate, wherein the thin film transistor includes a first electrode; a first contact hole pattern having a first width, wherein the first contact hole pattern exposes a portion of the first electrode, and a first contact hole to expose the portion of the first electrode, wherein an inner sidewall of the first contact hole pattern constitutes a first portion of the first contact hole.

Abstract translation: 根据本发明的示例性实施例的薄膜晶体管阵列面板包括：绝缘基板; 设置在所述绝缘基板上的薄膜晶体管，其中所述薄膜晶体管包括第一电极; 具有第一宽度的第一接触孔图案，其中所述第一接触孔图案暴露所述第一电极的一部分，以及第一接触孔，以暴露所述第一电极的所述部分，其中所述第一接触孔图案的内侧壁构成 第一接触孔的第一部分。

公开(公告)号：US09006742B2

公开(公告)日：2015-04-14

申请号：US13952059

申请日：2013-07-26

Applicant: Samsung Display Co., Ltd.

Inventor： Jeong Min Park ,  Dong-Won Woo ,  Je Hyeong Park ,  Sang Gab Kim ,  Jung-Soo Lee ,  Ji-Hyun Kim

IPC: H01L29/786 ,  H01L27/12

CPC classification number: H01L29/786 ,  H01L27/124 ,  H01L27/1259 ,  H01L29/78645

Abstract: A manufacturing method of a thin film transistor array panel includes: simultaneously forming a gate conductor and a first electrode on a substrate, using a non-peroxide-based etchant; forming a gate insulating layer on the gate conductor and the first electrode; forming a semiconductor, a source electrode, and a drain electrode on the gate insulating layer; forming a passivation layer on the semiconductor, the source electrode, and the drain electrode; and forming a second electrode layer on the passivation layer.

Abstract translation: 薄膜晶体管阵列板的制造方法包括：使用非过氧化物的蚀刻剂，在基板上同时形成栅极导体和第一电极; 在所述栅极导体和所述第一电极上形成栅极绝缘层; 在栅极绝缘层上形成半导体，源电极和漏电极; 在半导体，源电极和漏电极上形成钝化层; 以及在所述钝化层上形成第二电极层。

公开(公告)号：US20180157110A1

公开(公告)日：2018-06-07

申请号：US15831542

申请日：2017-12-05

Applicant: Samsung Display Co., Ltd.

Inventor： Jeong Min Park

IPC: G02F1/1335 ,  G02F1/1333 ,  H01L51/52 ,  G02B5/30

CPC classification number: G02F1/133528 ,  G02B5/3025 ,  G02F1/133308 ,  G02F1/13338 ,  G02F2001/133331 ,  G02F2201/503 ,  G02F2202/28 ,  H01L27/3244 ,  H01L51/0096 ,  H01L51/5237 ,  H01L51/5246 ,  H01L51/5281 ,  H01L51/5293

Abstract: A display device is provided. In the display device, a transparent adhesive layer is disposed between a polarizing layer and a window. The transparent adhesive layer has a planar size smaller than that of the polarizing layer. In addition, a reinforcing member is disposed on a back surface of the window, which corresponds to a non-display area of a first substrate of the display device.

公开(公告)号：US10978668B2

公开(公告)日：2021-04-13

申请号：US16443202

申请日：2019-06-17

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Gwui-Hyun Park ,  Pil Soon Hong ,  Chul Won Park ,  Jeong Min Park ,  Hyun Jin Son

IPC: H01L27/32 ,  H01L51/00 ,  H01L51/52 ,  C07F7/08 ,  C09J11/06

Abstract: An organic light emitting diode (OLED) display includes a first substrate, a second substrate facing the first substrate, a sealing member interposed between the first substrate and the second substrate, the sealing member including a siloxane material, a semiconductor layer on the first substrate, a planarization layer on the semiconductor layer, and a barrier rib on the planarization layer. The planarization layer or the barrier rib may also include the siloxane material.

公开(公告)号：US09741748B2

公开(公告)日：2017-08-22

申请号：US14989319

申请日：2016-01-06

Applicant: Samsung Display Co., Ltd.

Inventor： Jeong Min Park ,  Sung Kyun Park ,  Jung-Soo Lee ,  Ji-Hyun Kim ,  Jun Chun

IPC: H01L29/02 ,  G02F1/136 ,  H01L27/12 ,  H01L27/32 ,  H01L29/786 ,  G02F1/1343 ,  G02F1/1362 ,  H01L21/77

CPC classification number: H01L27/1248 ,  G02F1/134363 ,  G02F1/136227 ,  G02F2001/13629 ,  H01L27/124 ,  H01L27/1262 ,  H01L27/3248 ,  H01L27/3258 ,  H01L29/78606 ,  H01L2021/775

Abstract: A thin film transistor array panel includes a substrate, a gate line and a gate pad disposed on the substrate, a gate insulating layer disposed on the gate line and the gate pad, a data line and a data pad disposed on the gate insulating layer, an organic layer disposed on the data line and the data pad, and a connecting member disposed on one of the gate pad and the data pad, in which the organic layer includes a first portion overlapping the connecting member and a second portion not overlapping the connecting member, and a height of the first portion of the organic layer is greater than a height of the second portion of the organic layer.

公开(公告)号：US09515096B2

公开(公告)日：2016-12-06

申请号：US14838055

申请日：2015-08-27

Applicant: Samsung Display Co., Ltd.

Inventor： Jeong Min Park ,  Ji-Hyun Kim ,  Jung-Soo Lee ,  Sung Kyun Park

IPC: H01L27/12 ,  H01L33/58 ,  G02F1/1345 ,  G02F1/1362 ,  G02F1/1368 ,  H01L29/786

CPC classification number: H01L27/124 ,  G02F1/13458 ,  G02F1/136227 ,  G02F1/1368 ,  H01L27/1248 ,  H01L29/78669 ,  H01L29/78678 ,  H01L33/58

Abstract: The present disclosure provides a thin film transistor array. In an exemplary embodiment, the thin film transistor array includes: a substrate; a gate line including a gate pad and disposed on the substrate; a gate insulating layer disposed on the gate line and the gate pad; a data line including a data pad and disposed on the gate insulating layer; a first passivation layer disposed on the data line; a first electrode disposed on the first passivation layer; a second passivation layer disposed on the first electrode; and a second electrode disposed on the second passivation layer. The gate pad is exposed through a first contact hole, and the gate insulating layer, the first passivation layer, and the second passivation layer include at least a portion of the first contact hole.

Abstract translation: 本发明提供一种薄膜晶体管阵列。 在示例性实施例中，薄膜晶体管阵列包括：衬底; 栅极线，包括栅极焊盘并设置在所述衬底上; 设置在栅极线和栅极焊盘上的栅极绝缘层; 数据线，包括数据焊盘并设置在栅极绝缘层上; 设置在所述数据线上的第一钝化层; 设置在所述第一钝化层上的第一电极; 设置在所述第一电极上的第二钝化层; 以及设置在所述第二钝化层上的第二电极。 栅极焊盘通过第一接触孔露出，栅极绝缘层，第一钝化层和第二钝化层包括第一接触孔的至少一部分。

公开(公告)号：US20140183536A1

公开(公告)日：2014-07-03

申请号：US13915070

申请日：2013-06-11

Applicant: SAMSUNG DISPLAY, CO., LTD.

Inventor： Sung Kyun Park ,  Jeong Min Park ,  Jung-Soo Lee ,  Jin Ho Ju

IPC: H01L27/088 ,  H01L21/8234

CPC classification number: H01L27/124 ,  H01L27/1222 ,  H01L27/1248 ,  H01L27/1259

Abstract: A thin film transistor array panel according to an exemplary embodiment of the present invention includes: an insulation substrate; a thin film transistor disposed on the insulation substrate, wherein the thin film transistor includes a first electrode; a first contact hole pattern having a first width, wherein the first contact hole pattern exposes a portion of the first electrode, and a first contact hole to expose the portion of the first electrode, wherein an inner sidewall of the first contact hole pattern constitutes a first portion of the first contact hole.

Abstract translation: 根据本发明的示例性实施例的薄膜晶体管阵列面板包括：绝缘基板; 设置在所述绝缘基板上的薄膜晶体管，其中所述薄膜晶体管包括第一电极; 具有第一宽度的第一接触孔图案，其中所述第一接触孔图案暴露所述第一电极的一部分，以及第一接触孔，以暴露所述第一电极的所述部分，其中所述第一接触孔图案的内侧壁构成 第一接触孔的第一部分。