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    Semiconductor device
    11.
    发明授权
    Semiconductor device 有权

    公开(公告)号：US11894055B2

    公开(公告)日：2024-02-06

    申请号：US17578840

    申请日：2022-01-19

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Ansoo Park ,  Ahreum Kim ,  Homoon Shin

    IPC: G11C7/00 ,  G11C16/08 ,  G11C16/30

    CPC classification number: G11C16/08 ,  G11C16/30

    Abstract: A semiconductor device includes: a peripheral circuit region including circuit elements on a substrate, the circuit elements of a page buffer and a row decoder; and a cell region including gate electrode layers, stacked in a first direction, perpendicular to an upper surface of the substrate, and connected to the row decoder, and channel structures extending in the first direction to penetrate through the gate electrode layers and to be connected to the page buffer. The row decoder includes high-voltage elements, operating at a first power supply voltage, and low-voltage elements operating at a second power supply voltage, lower than the first power supply voltage. Among the high-voltage elements, at least one first high-voltage device is in a first well region doped with impurities having a first conductivity-type. At least one of the low-voltage elements is in a second well region surrounding the first well region and doped with impurities having a second conductivity-type, different from the first conductivity-type.

    Memory device including row decoders
    13.
    发明授权
    Memory device including row decoders 有权

    公开(公告)号：US11437088B2

    公开(公告)日：2022-09-06

    申请号：US17239655

    申请日：2021-04-25

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Youngjae Kim ,  Jincheol Kim ,  Ahreum Kim ,  Homoon Shin ,  Dooho Cho ,  Yongsung Cho

    IPC: G11C11/408 ,  G11C11/4074 ,  G11C11/4093 ,  G11C5/06

    Abstract: A nonvolatile memory includes; a memory cell array including memory cells commonly connected to a first signal line, a first row decoder including a first pass transistor configured to provide a driving voltage to one end of the first signal line, and a second row decoder including a second pass transistor configured to provide the driving voltage to an opposing end of the first signal line. An ON-resistance of the first pass transistor is different from an ON-resistance of the second pass transistor. A first wiring line having a first resistance connects the first pass transistor and the one end of the first signal line and a second wiring line having a second resistance different from the first resistance connects the second pass transistor and the opposing end of the first signal line.

    INTEGRATED CLOCK GATING CELL AND INTEGRATED CIRCUIT INCLUDING THE SAME
    14.
    发明申请
    INTEGRATED CLOCK GATING CELL AND INTEGRATED CIRCUIT INCLUDING THE SAME 有权

    公开(公告)号：US20210099173A1

    公开(公告)日：2021-04-01

    申请号：US16913484

    申请日：2020-06-26

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Ahreum Kim

    IPC: H03K19/00 ,  H03K3/037

    Abstract: A clock gating cell includes an input logic/latch circuit, a keeper logic/signal generating circuit, and an output driver. The input logic/latch circuit generates an internal enable signal based on first and second input enable signals, and generates a first internal signal provided to a first node based on the internal enable signal and an input clock signal. The keeper logic/signal generating circuit is connected between the first node and a second node, includes a feedback path feeding back the first internal signal, generates a second internal signal provided to the second node based on the first internal signal and the input clock signal, and includes first and second paths discharging the second node. The first and second paths are different. The second path is connected to the feedback path. The output driver generates an output clock signal based on the second internal signal.

    Voltage level shifter cell and integrated circuit including the same
    16.
    发明授权
    Voltage level shifter cell and integrated circuit including the same 有权

    公开(公告)号：US11728795B2

    公开(公告)日：2023-08-15

    申请号：US17564915

    申请日：2021-12-29

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Chanhee Park ,  Ahreum Kim ,  Minsu Kim

    IPC: H03K19/0175 ,  H03K3/356 ,  H01L27/02 ,  G06F30/30

    CPC classification number: H03K3/356113 ,  G06F30/30 ,  H01L27/0207 ,  H03K19/0175

    Abstract: A voltage level shifter cell, which is configured to convert voltage levels of input signals of multi-bits, includes: a first circuit area including a first voltage level shifter configured to convert a 1-bit first input signal from among the input signals; and a second circuit area including a second voltage level shifter configured to convert a 1-bit second input signal from among the input signals, wherein the first circuit area and the second circuit area share a first N-well to which a first power voltage is applied, and the first circuit area and the second circuit area share a second N-well to which a second power voltage is applied, wherein the first N-well is formed to extend in a first direction, and the first N-well and the second N-well are arranged to overlap in a second direction crossing the first direction.

    Integrated clock gating cell and integrated circuit including the same
    17.
    发明授权
    Integrated clock gating cell and integrated circuit including the same 有权

    公开(公告)号：US11368154B2

    公开(公告)日：2022-06-21

    申请号：US17192360

    申请日：2021-03-04

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Ahreum Kim

    IPC: H03K19/00 ,  H03K3/037

    Abstract: A clock gating cell includes an input logic/latch circuit, a keeper logic/signal generating circuit, and an output driver. The input logic/latch circuit generates an internal enable signal based on first and second input enable signals, and generates a first internal signal provided to a first node based on the internal enable signal and an input clock signal. The keeper logic/signal generating circuit is connected between the first node and a second node, includes a feedback path feeding back the first internal signal, generates a second internal signal provided to the second node based on the first internal signal and the input clock signal, and includes first and second paths discharging the second node. The first and second paths are different. The second path is connected to the feedback path. The output driver generates an output clock signal based on the second internal signal.

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