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    VERTICAL-TYPE MEMORY DEVICE
    11.
    发明申请
    VERTICAL-TYPE MEMORY DEVICE 审中-公开

    公开(公告)号：US20190244969A1

    公开(公告)日：2019-08-08

    申请号：US16108834

    申请日：2018-08-22

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Tak Lee ,  Su Bin Kang ,  Ji Mo Gu ,  Yu Jin Seo ,  Byoung Il Lee ,  Jun Ho Cha

    IPC: H01L27/11582 ,  H01L27/11568 ,  H01L29/10 ,  H01L29/423 ,  H01L27/11565 ,  H01L21/285

    Abstract: A vertical-type memory device includes a substrate having a cell array region and a connection region disposed adjacent to the cell array region, a plurality of gate electrode layers stacked on the cell array region and the connection region, a plurality of channel structures disposed in the cell array region, a plurality of dummy channel structures disposed in the connection region, and a plurality of slits disposed in the plurality of gate electrode layers in the cell array region. The plurality of gate electrode layers forms a stepped structure in the connection region, the plurality of channel structures penetrates the plurality of gate electrode layers, and the plurality of dummy channel structures penetrates at least one of the plurality of gate electrode layers.

    SEMICONDUCTOR MEMORY DEVICES AND METHODS FOR FABRICATING THE SAME
    14.
    发明申请
    SEMICONDUCTOR MEMORY DEVICES AND METHODS FOR FABRICATING THE SAME 有权

    公开(公告)号：US20210265389A1

    公开(公告)日：2021-08-26

    申请号：US17037074

    申请日：2020-09-29

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Joon Sung Kim ,  Byoung Il Lee ,  Seong-Hun Jeong ,  Jun Eon Jin

    IPC: H01L27/11582 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11573 ,  H01L27/11519 ,  H01L27/11526 ,  H01L23/522 ,  G11C7/18 ,  G11C8/14

    Abstract: A semiconductor memory device with improved reliability and a related method are provided. The semiconductor memory device includes a mold structure including a plurality of gate electrodes and a plurality of mold insulating films on a first substrate, a channel structure penetrating the mold structure and crossing a respective level of each of the gate electrodes, a plurality of first insulating patterns in the mold structure, the first insulating patterns including a material different from that of the mold insulating films, and a first through via in the first insulating patterns, the first through via penetrating the first substrate and the mold structure. The gate electrodes include a first word line and a second word line on the first word line. A first distance from the first word line to the first through via is different from a second distance from the second word line to the first through via.

    Semiconductor device including separation lines
    15.
    发明授权
    Semiconductor device including separation lines 有权

    公开(公告)号：US10998327B2

    公开(公告)日：2021-05-04

    申请号：US16227822

    申请日：2018-12-20

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Su Bin Kang ,  Byoung Il Lee ,  Ji Mo Gu ,  Yu Jin Seo ,  Tak Lee

    IPC: H01L27/11565 ,  H01L27/11524 ,  H01L27/11582 ,  H01L27/11519 ,  H01L27/1157 ,  H01L27/11556

    Abstract: A semiconductor device includes a stacked structure disposed on a substrate. The stacked structure includes a plurality of gate electrodes. The semiconductor device further includes a first structure disposed on the substrate and passing through the stacked structure, and a second structure disposed on the substrate. The second structure is disposed outside of the stacked structure, faces the first structure, and is spaced apart from the first structure. The first structure includes a plurality of separation lines passing through at least a portion of the plurality of gate electrodes and extending outside of the stacked structure, and the second structure is formed of the same material as the first structure.

    Three-dimensional semiconductor device having a memory block and separation structures
    16.
    发明授权
    Three-dimensional semiconductor device having a memory block and separation structures 有权

    公开(公告)号：US10978465B2

    公开(公告)日：2021-04-13

    申请号：US16227985

    申请日：2018-12-20

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Byoung Il Lee ,  Yu Jin Seo ,  Jun Eon Jin

    IPC: H01L27/11565 ,  H01L27/11524 ,  H01L27/11556 ,  H01L23/522 ,  H01L27/1157 ,  H01L27/11582 ,  H01L23/528 ,  H01L27/11519

    Abstract: A three-dimensional semiconductor device includes first and second extended regions disposed on a substrate spaced apart from each other, a memory block disposed on the substrate between the first and second extended regions, and first and second main separation structures disposed on the substrate spaced apart from each other. The first extended region, the memory block and the second extended region are disposed between the first and second main separation structures. The memory block includes data storage regions and word lines. The word lines extend from the memory block and pass through the first and second extended regions. A distance between the first and second main separation structures located on both sides of the first extended region is greater than a distance between the first and second main separation structures located on both sides of the memory block.

    Semiconductor device
    17.
    发明授权
    Semiconductor device 审中-公开

    公开(公告)号：US10672781B2

    公开(公告)日：2020-06-02

    申请号：US16724444

    申请日：2019-12-23

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Byoung Il Lee ,  Ji Mo Gu ,  Tak Lee ,  Jun Ho Cha

    IPC: H01L27/11556 ,  H01L27/11573 ,  H01L27/1157 ,  H01L27/11565 ,  H01L27/11548 ,  H01L27/11529 ,  H01L27/11582 ,  H01L27/11575

    Abstract: A semiconductor device includes a substrate having first and second regions, a gate electrode stack having a plurality of gate electrodes vertically stacked and spaced apart from each other in a first direction perpendicular to an upper surface of the substrate in the first region, and extending to have different lengths in a second direction parallel to the upper surface of the substrate from the first region to the second region, first and second isolation regions extending in the second direction perpendicular to the first direction, while penetrating through the gate electrode stack on the substrate, in the first and second regions, string isolation regions disposed between the first and second isolation regions in the first region, and extending in the second direction while penetrating through a portion of the gate electrode stack, and a plurality of auxiliary isolation regions disposed linearly with the string isolation regions in at least one of the first and second regions, and spaced apart from each other in the second direction.

    Vertical memory device
    19.
    发明授权
    Vertical memory device 有权

    公开(公告)号：US10204919B2

    公开(公告)日：2019-02-12

    申请号：US15252740

    申请日：2016-08-31

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Byoung Il Lee ,  Joong Shik Shin ,  Dong Seog Eun ,  Kyung Jun Shin ,  Hyun Kook Lee

    IPC: H01L27/115 ,  H01L27/11582 ,  H01L27/02 ,  H01L27/11565

    Abstract: A vertical memory device is provided as follows. A substrate has a cell array region and a connection region adjacent to the cell array region. A first gate stack includes gate electrode layers spaced apart from each other in a first direction perpendicular to the substrate. The gate electrode layers extends from the cell array region to the connection region in a second direction perpendicular to the first direction to form a first stepped structure on the connection region. The first stepped structure includes a first gate electrode layer and a second gate electrode layer sequentially stacked. The second gate electrode layer includes a first region having the same length as a length of the first gate electrode layer and a second region having a shorter length than the length of the first gate electrode layer.

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