公开(公告)号：US11456317B2

公开(公告)日：2022-09-27

申请号：US17023053

申请日：2020-09-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chanho Kim ,  Daeseok Byeon ,  Dongku Kang

IPC: H01L27/11573 ,  H01L27/11582 ,  G11C8/14 ,  H01L23/522 ,  H01L23/528 ,  H01L27/11526 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11565

Abstract: A memory device includes a peripheral circuit region comprising a first substrate, a plurality of metal layers over the first substrate, and a first metal pad, a cell region comprising a second substrate, a plurality of gate lines over the second substrate, a plurality of upper interconnection layers in the second substrate, and a second metal pad, wherein the cell region is vertically connected to the peripheral circuit region by the first metal pad and the second metal pad, a common source line between the second substrate and the plurality of gate lines, the common source line comprising a through hole, and a word line cut region extending across the plurality of gate lines and extending through the through hole of the common source line to be connected to a first upper interconnection layer from among the plurality of upper interconnection layers.

公开(公告)号：US20220277792A1

公开(公告)日：2022-09-01

申请号：US17746393

申请日：2022-05-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyunghwa Yun ,  Chanho Kim ,  Pansuk Kwak

IPC: G11C16/08 ,  G11C16/10 ,  H01L27/11582 ,  H01L27/1157 ,  H01L27/11573

Abstract: A memory device including: a memory cell array disposed in a first semiconductor layer, the memory cell array including a plurality of wordlines extended in a first direction and stacked in a second direction substantially perpendicular to the first direction; and a plurality of pass transistors disposed in the first semiconductor layer, wherein a first pass transistor of the plurality of pass transistors is disposed between a first signal line of a plurality of signal lines and a first wordline of the plurality of wordlines, and wherein the plurality of signal lines are arranged at the same level as a common source line.

公开(公告)号：US11270759B2

公开(公告)日：2022-03-08

申请号：US17006990

申请日：2020-08-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Chanho Kim ,  Daeseok Byeon ,  Hyunsurk Ryu

IPC: G11C5/06 ,  G11C11/4094 ,  G11C16/08 ,  G11C11/4093 ,  G11C11/408 ,  G06N3/063 ,  G11C16/04

Abstract: A flash memory device includes: first pads; second pads; third pads; a memory cell region including first metal pads and a memory cell array; and a peripheral circuit region including a second metal pads and vertically connected to the memory cell region by the first metal pads and the second metal pads directly. The peripheral circuit region includes a row decoder block; a buffer block storing a command and an address received from an external semiconductor chip through the first pads; a page buffer block connected to the memory cell array through bit lines, connected to the third pads through data lines, and exchanging data signals with the external semiconductor chip through the data lines and the third pads; and a control logic block receiving control signals from the external semiconductor chip through the second pads, and controlling the row decoder block and the page buffer block.

公开(公告)号：US20210065751A1

公开(公告)日：2021-03-04

申请号：US16816476

申请日：2020-03-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jooyong Park ,  Chanho Kim ,  Daeseok Byeon

IPC: G11C5/06 ,  G11C7/18 ,  G11C5/04

Abstract: A memory device includes a first semiconductor chip including a memory cell array disposed on a first substrate, and a first bonding metal on a first uppermost metal layer of the first semiconductor chip, and a second semiconductor chip including circuit devices disposed on a second substrate and a second bonding metal on a second uppermost metal layer of the second semiconductor chip, the circuit devices providing a peripheral circuit operating the memory cell array. The first and second semiconductor chips are electrically connected to each other by the first bonding metal and the second bonding metal in a bonding area. A routing wire electrically connected to the peripheral circuit is disposed in one or both of the first and second uppermost metal layers and is disposed in a non-bonding area in which the first and second semiconductor chips are not electrically connected to each other.

公开(公告)号：US10763278B2

公开(公告)日：2020-09-01

申请号：US16243837

申请日：2019-01-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyunghwa Yun ,  Pansuk Kwak ,  Chanho Kim ,  Junghwa Lee

IPC: H01L27/11582 ,  H01L23/528 ,  H01L23/535 ,  H01L27/11573

Abstract: A semiconductor memory device includes a substrate having a cell array region and a contact region, a stack structure including a plurality of gate electrodes on the cell array region and the contact region, a plurality of cell vertical channel structures extending through the stack structure on the cell array region, and a contact structure disposed beside of the stack structure on a top surface of the substrate and disposed along a line extending from the cell array region toward the contact region. The height of the contact structure on the cell array region is different from the height of the contact structure on the contact region.

公开(公告)号：US11875855B2

公开(公告)日：2024-01-16

申请号：US17746393

申请日：2022-05-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyunghwa Yun ,  Chanho Kim ,  Pansuk Kwak

IPC: G11C16/08 ,  G11C16/10 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40 ,  G11C16/04

CPC classification number: G11C16/08 ,  G11C16/0483 ,  G11C16/10 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40

Abstract: A memory device including: a memory cell array disposed in a first semiconductor layer, the memory cell array including a plurality of wordlines extended in a first direction and stacked in a second direction substantially perpendicular to the first direction; and a plurality of pass transistors disposed in the first semiconductor layer, wherein a first pass transistor of the plurality of pass transistors is disposed between a first signal line of a plurality of signal lines and a first wordline of the plurality of wordlines, and wherein the plurality of signal lines are arranged at the same level as a common source line.

公开(公告)号：US11699693B2

公开(公告)日：2023-07-11

申请号：US17545522

申请日：2021-12-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jooyong Park ,  Chanho Kim ,  Daeseok Byeon

IPC: H01L23/00 ,  H01L25/18 ,  H01L25/065

CPC classification number: H01L25/18 ,  H01L24/05 ,  H01L24/08 ,  H01L25/0657 ,  H01L2224/05147 ,  H01L2224/08145 ,  H01L2924/1431 ,  H01L2924/14511

Abstract: A memory device includes first and second chips. The first chip includes a memory cell array disposed on a first substrate, and first metal pads on a first uppermost metal layer of the first chip. The second chip includes peripheral circuits disposed on a second substrate, and second metal pads on a second uppermost metal layer of the second chip, the peripheral circuits operating the memory cell array. A first metal pad and a second metal pad are connected in a first area, the first metal pads being connected to the memory cell array and the second metal pad being connected to the peripheral circuits. A further first metal pad and a further second metal pad are connected in a second area, the further first metal pad being not connected to the memory cell array and the further second metal pad being connected to the peripheral circuits.

公开(公告)号：US20220352204A1

公开(公告)日：2022-11-03

申请号：US17860618

申请日：2022-07-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyunghwa YUN ,  Chanho Kim ,  Dongku Kang

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L27/11556 ,  H01L27/11519 ,  H01L27/11526 ,  H01L27/11573

Abstract: A nonvolatile memory device includes a peripheral circuit including a first active region and a memory block including a second active region on the peripheral circuit. The memory block includes a vertical structure including pairs of a first insulating layer and a first conductive layer, a second insulating layer on the vertical structure, a second conductive layer and a third conductive layer spaced apart from each other on the second insulating layer, first vertical channels and second vertical channels. The second conductive layer and the third conductive layer are connected with a first through via penetrating the vertical structure, the second active region, and a region of the second insulating layer that is exposed between the second conductive layer and the third conductive layer.

公开(公告)号：US11430802B2

公开(公告)日：2022-08-30

申请号：US17155525

申请日：2021-01-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Chanho Kim

IPC: H01L27/11 ,  G11C16/00 ,  H01L27/11573 ,  H01L25/065 ,  H01L25/18 ,  H01L23/00 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/11582 ,  G11C16/04 ,  G11C16/10 ,  G11C16/16 ,  G11C16/26 ,  H01L23/522

Abstract: A nonvolatile memory device includes bitlines, a source line, cell channel structures, a gate electrode structure, erase channel structures and an erase selection line. The bitlines are disposed at a first end portion of a cell region, arranged in a first horizontal direction and extend in a second horizontal direction. The source line is disposed at a second end portion of the cell region and extend in the second horizontal direction. The cell channel structures are disposed in a cell string area of the cell region and are respectively connected between the bitlines and the source line. The erase channel structures are disposed in a contact area of the cell region and respectively connected between the bitlines and the source line. The erase channel structures include erase transistors. The erase selection line is disposed in the contact area to form a gate electrode of the erase transistors.

公开(公告)号：US11329057B2

公开(公告)日：2022-05-10

申请号：US16944733

申请日：2020-07-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chanho Kim ,  Dongku Kang ,  Daeseok Byeon

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L27/112 ,  H01L27/11585 ,  H01L27/108 ,  H01L27/24

Abstract: An integrated circuit device includes a memory including a memory cell insulation surrounding a memory stack and a memory cell interconnection unit, a peripheral circuit including a peripheral circuit region formed on a peripheral circuit board, and a peripheral circuit interconnection between the peripheral circuit region and the memory structure, a plurality of conductive bonding structures on a boundary between the memory cell interconnection and the peripheral circuit interconnection in a first region, the first region overlapping the memory stack in a vertical direction, and a through electrode penetrating one of the memory cell insulation and the peripheral circuit board and extended to a lower conductive pattern included in the peripheral circuit interconnection in a second region, the second region overlapping the memory cell insulation in the vertical direction.