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    SEMICONDUCTOR DEVICES INCLUDING A STRESS PATTERN
    11.
    发明申请
    SEMICONDUCTOR DEVICES INCLUDING A STRESS PATTERN 有权

    公开(公告)号：US20220069128A1

    公开(公告)日：2022-03-03

    申请号：US17518741

    申请日：2021-11-04

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Sung Min Kim ,  Hyo Jin Kim ,  Dae Won Ha

    IPC: H01L29/78 ,  H01L21/762

    Abstract: Semiconductor devices are provided. A semiconductor device includes a fin structure including a stress structure and a semiconductor region that are sequentially stacked on a substrate. The semiconductor device includes a field insulation layer on a portion of the fin structure. The semiconductor device includes a gate electrode on the fin structure. Moreover, the stress structure includes an oxide.

    SEMICONDUCTOR DEVICES AND METHODS FOR FABRICATING THE SAME
    17.
    发明申请
    SEMICONDUCTOR DEVICES AND METHODS FOR FABRICATING THE SAME 有权

    公开(公告)号：US20220285493A1

    公开(公告)日：2022-09-08

    申请号：US17509646

    申请日：2021-10-25

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Mun Hyeon Kim ,  Kern Rim ,  Dae Won Ha

    IPC: H01L29/06 ,  H01L29/78 ,  H01L29/66 ,  H01L29/786 ,  H01L21/8234

    Abstract: A semiconductor device is provided. The semiconductor device includes a substrate, an active pattern extending in a first horizontal direction on the substrate, a gate electrode extending in a second horizontal direction different from the first horizontal direction on the active pattern, a source/drain region on at least one side of the gate electrode, a source/drain contact extending into the source/drain region and including a filling layer and a barrier layer along a sidewall of the filling layer, and a silicide layer between the source/drain region and the filling layer, the silicide layer including a first sidewall in contact with the filling layer and a second sidewall in contact with the source/drain region, wherein the barrier layer is not between the filling layer and the source/drain region.

    SEMICONDUCTOR DEVICE INCLUDING CONTACT STRUCTURE
    18.
    发明申请
    SEMICONDUCTOR DEVICE INCLUDING CONTACT STRUCTURE 有权

    公开(公告)号：US20210375692A1

    公开(公告)日：2021-12-02

    申请号：US17398623

    申请日：2021-08-10

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： HWI CHAN JUN ,  Chang Hwa Kim ,  Dae Won Ha

    IPC: H01L21/8234 ,  H01L29/66 ,  H01L29/78 ,  H01L23/522 ,  H01L27/088

    Abstract: A semiconductor device including a contact structure is provided. The semiconductor device includes an isolation region defining a lower active region. First and second source/drain regions and first and second gate electrodes are on the lower active region. The first and second source/drain regions are adjacent to each other. First and second gate capping patterns are on the first and second gate electrodes, respectively. First and second contact structures are on the first and second source/drain regions, respectively. A lower insulating pattern is between the first and second source/drain regions. An upper insulating pattern is between the first and second contact structures. Silicon oxide has etching selectivity with respect to an insulating material which the upper insulating pattern, the first gate capping pattern, and the second gate capping pattern are formed of.

    Semiconductor device and method for fabricating the same
    20.
    发明授权
    Semiconductor device and method for fabricating the same 有权

    公开(公告)号：US12266656B2

    公开(公告)日：2025-04-01

    申请号：US17210751

    申请日：2021-03-24

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Mun Hyeon Kim ,  Sung Min Kim ,  Dae Won Ha

    IPC: H01L27/092 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786

    Abstract: A semiconductor device includes a substrate with first and second regions separated from each other, a laminate structure including at least one sacrificial layer and at least one active layer alternately stacked on the substrate, a first isolation insulating layer on the laminate structure on the first region, a second isolation insulating layer on the laminate structure on the second region, the second isolation insulating layer having a same thickness as the first isolation insulating layer, a first upper active pattern spaced apart from the first isolation insulating layer, a first gate electrode surrounding at least a portion of the first upper active pattern, a second upper active pattern spaced apart from the second isolation insulating layer, and a second gate electrode surrounding at least a portion of the second upper active pattern, wherein top surfaces of the first and second isolation insulating layers are at different heights.

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