公开(公告)号：US20230058991A1

公开(公告)日：2023-02-23

申请号：US17690178

申请日：2022-03-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yang XU ,  Nam Kyu CHO ,  Seok Hoon KIM ,  Yong Seung KIM ,  Pan Kwi PARK ,  Dong Suk SHIN ,  Sang Gil LEE ,  Si Hyung LEE

IPC: H01L29/78 ,  H01L27/088 ,  H01L29/417 ,  H01L29/06

Abstract: A semiconductor device including first fin-shaped patterns in a first region of a substrate and spaced apart from each other in a first direction, second fin-shaped patterns in a second region of the substrate and spaced apart from each other in a second direction, a first field insulating film on the substrate and covering sidewalls of the first fin-shaped patterns, a second field insulating film on the substrate and covering sidewalls of the second fin-shaped patterns, a first source/drain pattern on the first field insulating film, connected to the first fin-shaped patterns, and including a first silicon-germanium pattern, and a second source/drain pattern on the second field insulating film, connected to the second fin-shaped patterns, and including a second silicon-germanium pattern, the second source/drain pattern and the second field insulating film defining one or more first air gaps therebetween may be provided.

公开(公告)号：US20220181498A1

公开(公告)日：2022-06-09

申请号：US17391342

申请日：2021-08-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung Taek KIM ,  Seok Hoon KIM ,  Ryong HA ,  Pan Kwi PARK ,  Dong Suk SHIN

IPC: H01L29/786 ,  H01L29/66

Abstract: There is provided a semiconductor device comprising an active pattern, including a lower pattern extending in a first direction, and a plurality of sheet patterns spaced apart from the lower pattern in a second direction perpendicular to the first direction, a plurality of gate structures on the lower pattern to be spaced apart from each other in the first direction and including a gate electrode and a gate insulating film wrapping the plurality of sheet patterns, a source/drain recess defined between the gate structures adjacent to each other, and a source/drain pattern inside the source/drain recess and including a semiconductor blocking film formed continuously along the source/drain recess, wherein the source/drain recesses include a plurality of width extension regions, and a width of each of the width extension regions in the first direction increases and then decreases, as it goes away from an upper surface of the lower pattern.

公开(公告)号：US20190067484A1

公开(公告)日：2019-02-28

申请号：US15995414

申请日：2018-06-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seok Hoon KIM ,  Dong Myoung KIM ,  Dong Suk SHIN ,  Seung Hun LEE ,  Cho Eun LEE ,  Hyun Jung LEE ,  Sung Uk JANG ,  Edward Nam Kyu CHO ,  Min-Hee CHOI

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/423 ,  H01L21/8234 ,  H01L21/768 ,  H01L21/02

Abstract: A semiconductor device includes a first fin type pattern on a substrate, a second fin type pattern, parallel to the first fin type pattern, on the substrate, and an epitaxial pattern on the first and second fin type patterns. The epitaxial pattern may include a shared semiconductor pattern on the first fin type pattern and the second fin type pattern. The shared semiconductor pattern may include a first sidewall adjacent to the first fin type pattern and a second sidewall adjacent to the second fin type pattern. The first sidewall may include a first lower facet, a first upper facet on the first lower facet and a first connecting curved surface connecting the first lower and upper facets. The second sidewall may include a second lower facet, a second upper facet on the second lower facet and a second connecting curved surface connecting the second lower and upper facets.

公开(公告)号：US20170345911A1

公开(公告)日：2017-11-30

申请号：US15479459

申请日：2017-04-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyun Kwan YU ,  Kyung Ho KIM ,  Dong Suk SHIN

IPC: H01L29/49 ,  H01L29/66 ,  H01L29/165 ,  H01L29/161 ,  H01L29/06 ,  H01L29/08 ,  H01L21/8238 ,  H01L27/11 ,  H01L27/092 ,  H01L29/78 ,  H01L29/16

CPC classification number: H01L29/4983 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823468 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823864 ,  H01L21/823878 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/1104 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/7848 ,  H01L29/785

Abstract: A semiconductor device includes a field insulating film including a first region and a second region on a substrate, a recess in the first region of the field insulating film, a gate electrode on the second region of the field insulating film, and a gate spacer along a sidewall of the gate electrode and a sidewall of the recess.

公开(公告)号：US20170263722A1

公开(公告)日：2017-09-14

申请号：US15408815

申请日：2017-01-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jung Gun YOU ,  Gi Gwan PARK ,  Sug Hyun SUNG ,  Myung Yoon UM ,  Dong Suk SHIN

IPC: H01L29/417 ,  H01L27/088 ,  H01L29/78

CPC classification number: H01L29/41791 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/775 ,  H01L29/7848

Abstract: A semiconductor device includes a first gate electrode on a substrate, a first trench on a first side of the first gate electrode, a second trench on a second side of the first gate electrode, a depth of the second trench being greater than a depth of the first trench, a first source/drain filling the first trench, and a second source/drain filling the second trench, a height of an upper surface of the second source/drain being greater than a height of the first source/drain.

公开(公告)号：US20170092728A1

公开(公告)日：2017-03-30

申请号：US15272456

申请日：2016-09-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ki Hwan KIM ,  Jung Gun YOU ,  Gi Gwan PARK ,  Dong Suk SHIN ,  Jin Wook KIM

IPC: H01L29/417 ,  H01L29/78 ,  H01L29/45 ,  H01L27/088

CPC classification number: H01L29/41791 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823821 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/0673 ,  H01L29/456 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: A semiconductor device includes a substrate having first and second regions, a first fin-type pattern and a second fin-type pattern formed in the first region and extending in a first direction, and a third fin-type pattern and a fourth fin-type pattern formed in the second region and extending in a third direction. A first source/drain is formed on the first fin-type pattern and a second source/drain region is formed on the second fin-type pattern. Each of first and second source/drains have a cross section defining a same convex polygonal shape. A third source/drain is formed on the third fin-type pattern and a fourth source/drain region is formed on the fourth fin-type pattern. Cross-sections of the third and fourth source/drains define different convex polygonal shapes from one another.