公开(公告)号：US20230387206A1

公开(公告)日：2023-11-30

申请号：US18117262

申请日：2023-03-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ki Hwan KIM ,  Kyung Ho KIM ,  Kang Hun MOON ,  Cho Eun LEE ,  Yong Uk JEON

IPC: H01L29/08 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L29/775 ,  H01L29/66

CPC classification number: H01L29/0847 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/4991 ,  H01L29/775 ,  H01L29/66545 ,  H01L29/66439

Abstract: A semiconductor device comprises an active pattern including a lower pattern and a plurality of sheet patterns that are spaced apart from the lower pattern in a first direction, a plurality of gate structures disposed on the lower pattern to be spaced apart from each other in a second direction, each of the gate structures including a gate electrode and gate insulating films, source/drain recesses defined between adjacent gate structures and a source/drain pattern filling the source/drain recesses. Each source/drain pattern may include a first semiconductor liner, which extend along sidewalls and a bottom surface of the source/drain recesses, second semiconductor liners, which are on the first semiconductor liners and extend along the sidewalls and the bottom surface of the source/drain recesses, and a filling semiconductor film, which is on the second semiconductor liners and fills the source/drain recess. The second semiconductor liners may be doped with carbon, and the first semiconductor liners may be in contact with the lower pattern and the sheet patterns, while the first semiconductor liners may include carbon-undoped regions.

公开(公告)号：US20180114791A1

公开(公告)日：2018-04-26

申请号：US15850183

申请日：2017-12-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ki Hwan KIM ,  Gi Gwan PARK ,  Jung Gun YOU ,  Dong Suk SHIN ,  Hyun Yul CHOI

IPC: H01L27/092 ,  H01L21/84 ,  H01L27/02 ,  H01L27/088 ,  H01L27/12 ,  H01L29/06 ,  H01L29/08 ,  H01L29/165 ,  H01L29/167 ,  H01L29/417 ,  H01L29/45 ,  H01L29/78

CPC classification number: H01L27/0924 ,  H01L21/823425 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0207 ,  H01L27/0886 ,  H01L27/092 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/167 ,  H01L29/41766 ,  H01L29/41783 ,  H01L29/41791 ,  H01L29/456 ,  H01L29/78 ,  H01L29/7848 ,  H01L29/785

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate comprising first and second regions, in the first region, first and second gate electrodes formed parallel to each other on the substrate, and being spaced apart from each other by a first distance, in the second region, third and fourth gate electrodes formed parallel to each other on the substrate, and being spaced apart from each other by a second distance which is greater than the first distance, in the first region, a first recess formed on the substrate between the first and second gate electrodes, in the second region, a second recess formed on the substrate between the third and fourth gate electrodes, a first epitaxial source/drain filling the first recess and a second epitaxial source/drain filling the second recess, wherein an uppermost portion of an upper surface of the first epitaxial source/drain is higher than an uppermost portion of an upper surface of the second epitaxial source/drain.

公开(公告)号：US20250022959A1

公开(公告)日：2025-01-16

申请号：US18901222

申请日：2024-09-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung Uk JANG ,  Young Dae CHO ,  Ki Hwan KIM ,  Su Jin JUNG

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/423 ,  H01L29/786

Abstract: A semiconductor device includes an active region extending in a first direction on a substrate, channel layers on the active region and spaced apart vertically, a gate structure intersecting the active region and the channel layers, the gate structure extending in a second direction and surrounding the channel layers, and a source/drain region on the active region at a side of the gate structure, the source/drain region contacting the channel layers, the source/drain region including first epitaxial layers having a first composition and including first layers on side surfaces of the channel layers and a second layer on the active region at a lower end of the source/drain region, and a second epitaxial layer having a second composition different from the first composition, the second epitaxial layer being between the first epitaxial layers in the first direction and being between the first epitaxial layers vertically in a third direction.

公开(公告)号：US20240063306A1

公开(公告)日：2024-02-22

申请号：US18498901

申请日：2023-10-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Su Jin JUNG ,  Ki Hwan KIM ,  Sung Uk JANG ,  Young Dae CHO

IPC: H01L29/786 ,  H01L21/02 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L29/78618 ,  H01L21/0259 ,  H01L29/0665 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66742 ,  H01L29/78696

Abstract: A semiconductor device is provided. The semiconductor comprises an active pattern including a lower pattern and a plurality of sheet patterns that are spaced apart from the lower pattern in a first direction, a source/drain pattern on the lower pattern and in contact with the plurality of sheet patterns, and a gate structure on opposing sides of the source/drain pattern in a second direction different from the first direction, the gate structure including a gate electrode on the plurality of sheet patterns, wherein the source/drain pattern includes an epitaxial region that comprises a semiconductor material and a cavity region that is inside the epitaxial region and that is surrounded by the semiconductor material.

公开(公告)号：US20230387205A1

公开(公告)日：2023-11-30

申请号：US18100233

申请日：2023-01-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ki Hwan KIM ,  KYUNGHO KIM ,  KANG HUN MOON ,  CHOEUN LEE ,  Yonguk JEON

IPC: H01L29/08 ,  H01L29/66

CPC classification number: H01L29/0847 ,  H01L29/6656

Abstract: A semiconductor device includes a substrate including an active pattern; a source/drain pattern on the active pattern; a gate electrode on the active pattern; and a gate spacer on the source/drain pattern. The source/drain pattern includes a first semiconductor layer on the active pattern and a second semiconductor layer on the first semiconductor layer. The first semiconductor layer includes a first inner sidewall and second inner sidewall on the second semiconductor layer. A distance between the first and second inner sidewalls of the first semiconductor layer decreases according as positions of two portions of the first semiconductor layer where the distance is measured become closer to the gate spacer decreases.

公开(公告)号：US20220157990A1

公开(公告)日：2022-05-19

申请号：US17587402

申请日：2022-01-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sung Uk JANG ,  Ki Hwan KIM ,  Su Jin JUNG ,  Bong Soo KIM ,  Young Dae CHO

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/08 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02 ,  H01L29/24

Abstract: A semiconductor device including an active region extending in a first direction on a substrate; a gate structure intersecting the active region and extending in a second direction on the substrate; and a source/drain region on the active region and at least one side of the gate structure, wherein the source/drain region includes a plurality of first epitaxial layers spaced apart from each other in the first direction, the plurality of first epitaxial layers including first impurities of a first conductivity type; and a second epitaxial layer filling a space between the plurality of first epitaxial layers, the second epitaxial layer including second impurities of the first conductivity type.

公开(公告)号：US20210296499A1

公开(公告)日：2021-09-23

申请号：US17337759

申请日：2021-06-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sung Uk JANG ,  Young Dae CHO ,  Ki Hwan KIM ,  Su Jin JUNG

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/786 ,  H01L29/423

Abstract: A semiconductor device includes an active region extending in a first direction on a substrate, channel layers on the active region and spaced apart vertically, a gate structure intersecting the active region and the channel layers, the gate structure extending in a second direction and surrounding the channel layers, and a source/drain region on the active region at a side of the gate structure, the source/drain region contacting the channel layers, the source/drain region including first epitaxial layers having a first composition and including first layers on side surfaces of the channel layers and a second layer on the active region at a lower end of the source/drain region, and a second epitaxial layer having a second composition different from the first composition, the second epitaxial layer being between the first epitaxial layers in the first direction and being between the first epitaxial layers vertically in a third direction.

公开(公告)号：US20200220018A1

公开(公告)日：2020-07-09

申请号：US16708717

申请日：2019-12-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sung Uk JANG ,  Young Dae CHO ,  Ki Hwan KIM ,  Su Jin JUNG

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/786 ,  H01L29/08

Abstract: A semiconductor device includes an active region extending in a first direction on a substrate, channel layers on the active region and spaced apart vertically, a gate structure intersecting the active region and the channel layers, the gate structure extending in a second direction and surrounding the channel layers, and a source/drain region on the active region at a side of the gate structure, the source/drain region contacting the channel layers, the source/drain region including first epitaxial layers having a first composition and including first layers on side surfaces of the channel layers and a second layer on the active region at a lower end of the source/drain region, and a second epitaxial layer having a second composition different from the first composition, the second epitaxial layer being between the first epitaxial layers in the first direction and being between the first epitaxial layers vertically in a third direction.

公开(公告)号：US20200220015A1

公开(公告)日：2020-07-09

申请号：US16598012

申请日：2019-10-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sung Uk JANG ,  Ki Hwan KIM ,  Su Jin JUNG ,  Bong Soo KIM ,  Young Dae CHO

IPC: H01L29/78 ,  H01L29/24 ,  H01L29/08 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L29/66 ,  H01L21/02

Abstract: A semiconductor device including an active region extending in a first direction on a substrate; a gate structure intersecting the active region and extending in a second direction on the substrate; and a source/drain region on the active region and at least one side of the gate structure, wherein the source/drain region includes a plurality of first epitaxial layers spaced apart from each other in the first direction, the plurality of first epitaxial layers including first impurities of a first conductivity type; and a second epitaxial layer filling a space between the plurality of first epitaxial layers, the second epitaxial layer including second impurities of the first conductivity type.

公开(公告)号：US20170092728A1

公开(公告)日：2017-03-30

申请号：US15272456

申请日：2016-09-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ki Hwan KIM ,  Jung Gun YOU ,  Gi Gwan PARK ,  Dong Suk SHIN ,  Jin Wook KIM

IPC: H01L29/417 ,  H01L29/78 ,  H01L29/45 ,  H01L27/088

CPC classification number: H01L29/41791 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823821 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/0673 ,  H01L29/456 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: A semiconductor device includes a substrate having first and second regions, a first fin-type pattern and a second fin-type pattern formed in the first region and extending in a first direction, and a third fin-type pattern and a fourth fin-type pattern formed in the second region and extending in a third direction. A first source/drain is formed on the first fin-type pattern and a second source/drain region is formed on the second fin-type pattern. Each of first and second source/drains have a cross section defining a same convex polygonal shape. A third source/drain is formed on the third fin-type pattern and a fourth source/drain region is formed on the fourth fin-type pattern. Cross-sections of the third and fourth source/drains define different convex polygonal shapes from one another.