公开(公告)号：US11791137B2

公开(公告)日：2023-10-17

申请号：US16855048

申请日：2020-04-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hakseung Lee ,  Ho-Jin Lee ,  Dong-Chan Lim ,  Jinnam Kim ,  Kwangjin Moon

IPC: H01J37/32 ,  H01L21/67

CPC classification number: H01J37/32642 ,  H01J37/32715 ,  H01L21/67069 ,  H01J2237/334

Abstract: A bevel etching apparatus includes a chuck plate that is configured to receive a substrate, a lower ring surrounding a circumference of the chuck plate, a cover plate on the chuck plate, and an upper ring surrounding a circumference of the cover plate. The lower ring includes a ring base and a protrusion that extends upwardly from an edge of the ring base and surrounds a lower portion of a sidewall of the substrate.

公开(公告)号：US11374001B2

公开(公告)日：2022-06-28

申请号：US16851476

申请日：2020-04-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sunyoung Noh ,  Wandon Kim ,  Hyunbae Lee ,  Donggon Yoo ,  Dong-Chan Lim

IPC: H01L27/088 ,  H01L23/528 ,  H01L23/532 ,  H01L29/06 ,  H01L21/321 ,  H01L21/768 ,  H01L21/8234 ,  H01L23/535

Abstract: A semiconductor device includes an interlayer dielectric layer on a substrate, a first connection line that fills a first trench of the interlayer dielectric layer, the first trench having a first width, and a second connection line that fills a second trench of the interlayer dielectric layer, the second trench having a second width greater than the first width, and the second connection line including a first metal layer that covers an inner sidewall of the second trench, a barrier layer that covers a bottom surface of the second trench, and a second metal layer on the first metal layer and the barrier layer, the first connection line and the first metal layer include a first metal, and the second metal layer includes a second metal different from the first metal.

公开(公告)号：US20210183822A1

公开(公告)日：2021-06-17

申请号：US17190113

申请日：2021-03-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hak-Seung LEE ,  Kwang-Jin Moon ,  Tae-Seong Kim ,  Dae-Suk Lee ,  Dong-Chan Lim

IPC: H01L25/065 ,  H01L23/31 ,  H01L23/48 ,  H01L23/522 ,  H01L23/528 ,  H01L23/00 ,  H01L25/00

Abstract: A semiconductor package includes a first semiconductor chip and a second semiconductor chip stacked on the first semiconductor chip. The first semiconductor chip includes a substrate having a first via hole, an insulation interlayer formed on the substrate and having a first bonding pad in an outer surface thereof and a second via hole connected to the first via hole and exposing the first bonding pad, and a plug structure formed within the first and second via holes to be connected to the first bonding pad. The second semiconductor chip includes a second bonding pad bonded to the plug structure which is exposed from a surface of the substrate of the first semiconductor chip.

公开(公告)号：US20210066386A1

公开(公告)日：2021-03-04

申请号：US16855048

申请日：2020-04-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hakseung Lee ,  Ho-Jin Lee ,  Dong-Chan Lim ,  Jinnam Kim ,  Kwangjin Moon

IPC: H01L27/146 ,  H01L21/67 ,  H01J37/32

Abstract: A bevel etching apparatus includes a chuck plate that is configured to receive a substrate, a lower ring surrounding a circumference of the chuck plate, a cover plate on the chuck plate, and an upper ring surrounding a circumference of the cover plate. The lower ring includes a ring base and a protrusion that extends upwardly from an edge of the ring base and surrounds a lower portion of a sidewall of the substrate.

公开(公告)号：US20200161277A1

公开(公告)日：2020-05-21

申请号：US16430625

申请日：2019-06-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hak-Seung LEE ,  Kwang-Jin Moon ,  Tae-Seong Kim ,  Dae-Suk Lee ,  Dong-Chan Lim

IPC: H01L25/065 ,  H01L23/48 ,  H01L23/522 ,  H01L23/528 ,  H01L23/31 ,  H01L23/00 ,  H01L25/00

Abstract: A semiconductor package includes a first semiconductor chip and a second semiconductor chip stacked on the first semiconductor chip. The first semiconductor chip includes a substrate having a first via hole, an insulation interlayer formed on the substrate and having a first bonding pad in an outer surface thereof and a second via hole connected to the first via hole and exposing the first bonding pad, and a plug structure formed within the first and second via holes to be connected to the first bonding pad. The second semiconductor chip includes a second bonding pad bonded to the plug structure which is exposed from a surface of the substrate of the first semiconductor chip.