公开(公告)号：US10446774B2

公开(公告)日：2019-10-15

申请号：US15870922

申请日：2018-01-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yi-Koan Hong ,  Kwang-Jin Moon ,  Nae-In Lee ,  Ho-Jin Lee

IPC: H01L23/48 ,  H01L51/44 ,  H01L25/065 ,  H01L23/532 ,  H01L23/538 ,  H01L21/768 ,  H01L51/00 ,  H01L23/00 ,  B82Y99/00 ,  B82Y10/00

Abstract: A semiconductor device includes a first conductive pattern at an upper portion of a first insulating interlayer on a first substrate, a first plurality of conductive nanotubes (CNTs) extending vertically, a second conductive pattern at a lower portion of a second insulating interlayer beneath a second substrate, and a second plurality of CNTs extending vertically. A lower surface of the second insulating interlayer contacts an upper surface of the first insulating interlayer. At least a portion of a sidewall of each of the first plurality of CNTs is covered by the first conductive pattern, and at least a portion of a sidewall of each of the second plurality of CNTs is covered by the second conductive pattern. The first and second conductive patterns vertically face each other, and at least one of the first plurality of CNTs and at least one of the second plurality of CNTs contact each other.

公开(公告)号：US10049997B2

公开(公告)日：2018-08-14

申请号：US15440621

申请日：2017-02-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ju-Il Choi ,  Hyoju Kim ,  Kwangjin Moon ,  Sujeong Park ,  Jubin Seo ,  Naein Lee ,  Ho-Jin Lee

IPC: H01L23/00

Abstract: A pad is disposed on a substrate. A bump structure is disposed on the pad and electrically connected to the pad. The bump structure includes a first copper layer and a second copper layer sequentially stacked on the pad and a solder ball on the second copper layer. A first X-ray diffraction (XRD) peak intensity ratio of (111) plane to (200) plane of the first copper layer is greater than a second XRD peak intensity ratio of (111) plane to (200) plane of the second copper layer.

公开(公告)号：US11791137B2

公开(公告)日：2023-10-17

申请号：US16855048

申请日：2020-04-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hakseung Lee ,  Ho-Jin Lee ,  Dong-Chan Lim ,  Jinnam Kim ,  Kwangjin Moon

IPC: H01J37/32 ,  H01L21/67

CPC classification number: H01J37/32642 ,  H01J37/32715 ,  H01L21/67069 ,  H01J2237/334

Abstract: A bevel etching apparatus includes a chuck plate that is configured to receive a substrate, a lower ring surrounding a circumference of the chuck plate, a cover plate on the chuck plate, and an upper ring surrounding a circumference of the cover plate. The lower ring includes a ring base and a protrusion that extends upwardly from an edge of the ring base and surrounds a lower portion of a sidewall of the substrate.

公开(公告)号：US20210066386A1

公开(公告)日：2021-03-04

申请号：US16855048

申请日：2020-04-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hakseung Lee ,  Ho-Jin Lee ,  Dong-Chan Lim ,  Jinnam Kim ,  Kwangjin Moon

IPC: H01L27/146 ,  H01L21/67 ,  H01J37/32

Abstract: A bevel etching apparatus includes a chuck plate that is configured to receive a substrate, a lower ring surrounding a circumference of the chuck plate, a cover plate on the chuck plate, and an upper ring surrounding a circumference of the cover plate. The lower ring includes a ring base and a protrusion that extends upwardly from an edge of the ring base and surrounds a lower portion of a sidewall of the substrate.

公开(公告)号：US10580726B2

公开(公告)日：2020-03-03

申请号：US16106645

申请日：2018-08-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jin-Ho Chun ,  Seong-Min Son ,  Hyung-Jun Jeon ,  Kwang-Jin Moon ,  Jin-Ho An ,  Ho-Jin Lee ,  Atsushi Fujisaki

IPC: H01L23/498 ,  H01L23/525 ,  H01L23/532 ,  H01L23/31 ,  H01L23/00 ,  H01L21/768 ,  H01L23/48

Abstract: A semiconductor device and a method of manufacturing the same, the device including a through-hole electrode structure extending through a substrate; a redistribution layer on the through-hole electrode structure; and a conductive pad, the conductive pad including a penetrating portion extending through the redistribution layer; and a protrusion portion on the penetrating portion, the protrusion portion protruding from an upper surface of the redistribution layer, wherein a central region of an upper surface of the protrusion portion is flat and not closer to the substrate than an edge region of the upper surface of the protrusion portion.

公开(公告)号：US20180108540A1

公开(公告)日：2018-04-19

申请号：US15636849

申请日：2017-06-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jae-Hyun Phee ,  Ho-Jin Lee ,  Taeseong Kim ,  Kwangjin Moon ,  Jin Ho An ,  Naein Lee

IPC: H01L21/48 ,  H01L23/498 ,  H01L21/683 ,  H01L23/64 ,  H01L23/00 ,  H05K3/40 ,  H05K1/16

CPC classification number: H01L21/486 ,  H01L21/6835 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/544 ,  H01L23/642 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/48 ,  H01L24/81 ,  H01L2223/54426 ,  H01L2224/13101 ,  H01L2224/16227 ,  H01L2224/48227 ,  H01L2224/81203 ,  H01L2224/81815 ,  H01L2924/00014 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/1438 ,  H01L2924/14511 ,  H01L2924/1461 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/37001 ,  H05K1/162 ,  H05K3/4038 ,  H01L2924/014 ,  H01L2224/45099

Abstract: A method of manufacturing a semiconductor package including forming a photoresist pattern on a first surface of an interposer substrate. The interposer substrate includes an electrode zone and a scribe line zone. The interposer substrate is etched using the photoresist pattern as a mask to form a first opening and a second opening respectively on the electrode zone and the scribe line zone. An insulation layer and a conductive layer are formed on the first surface of the interposer substrate. A width of the second opening is smaller than a width of the first opening. The insulation layer contacts each of the first surface of the interposer substrate, an inner surface of the first opening, and an inner surface of the second opening.

公开(公告)号：US09236349B2

公开(公告)日：2016-01-12

申请号：US13943828

申请日：2013-07-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyu-Ha Lee ,  Pil-Kyu Kang ,  Tae-Yeong Kim ,  Ho-Jin Lee ,  Byung-Lyul Park ,  Gil-Heyun Choi

IPC: H01L23/538 ,  H01L23/485 ,  H01L23/48 ,  H01L23/00 ,  H01L21/683 ,  H01L21/768 ,  H01L23/525 ,  H01L23/532

CPC classification number: H01L23/5384 ,  H01L21/6836 ,  H01L21/76834 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/485 ,  H01L23/525 ,  H01L23/53238 ,  H01L24/00 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L2224/02331 ,  H01L2224/02372 ,  H01L2224/03002 ,  H01L2224/0346 ,  H01L2224/0347 ,  H01L2224/0401 ,  H01L2224/05024 ,  H01L2224/05027 ,  H01L2224/0508 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05176 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05186 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/06182 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/13091 ,  H01L2924/00 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/01074

Abstract: Semiconductor device including through via structure and redistribution structures is provided. The semiconductor device may include internal circuits on a first side of a substrate, a through via structure vertically penetrating the substrate to be electrically connected to one of the internal circuits, a redistribution structure on a second side of the substrate and electrically connected to the through via structure, and an insulating layer between the second side of the substrate and the redistribution structure. The redistribution structure may include a redistribution barrier layer and a redistribution metal layer, and the redistribution barrier layer may extend on a bottom surface of the redistribution metal layer and may partially surround a side of the redistribution metal layer.

Abstract translation: 提供了包括通孔结构和再分配结构的半导体器件。 半导体器件可以包括在衬底的第一侧上的内部电路，垂直穿过衬底以与内部电路中的一个电连接的通孔结构，在衬底的第二侧上的再分配结构，并且电连接到通孔 通孔结构，以及在基板的第二面和再分布结构之间的绝缘层。 再分布结构可以包括再分配阻挡层和再分布金属层，再分布阻挡层可以在再分布金属层的底表面上延伸并且可以部分地围绕再分布金属层的一侧。

公开(公告)号：US20140110894A1

公开(公告)日：2014-04-24

申请号：US13964433

申请日：2013-08-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ho-Jin Lee ,  Pil-kyu Kang ,  Taeyeong Kim ,  Byung Lyul Park ,  Kyu-Ha Lee ,  Gilheyun Choi

IPC: H01L21/683

CPC classification number: H01L21/6835 ,  H01L24/03 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/92 ,  H01L24/94 ,  H01L2221/68318 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/0401 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/92 ,  H01L2224/9222 ,  H01L2224/92222 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2924/15311 ,  H01L2224/03 ,  H01L2924/014 ,  H01L2224/11 ,  H01L2221/68304 ,  H01L21/304 ,  H01L2221/68381 ,  H01L21/78 ,  H01L2224/81

Abstract: A wafer carrier includes a base having a cavity provided at the center of the base and an outer sidewall extending along and away from an edge of the base to define the cavity. The cavity is configured to be filled with an adhesive layer. The wafer carrier is configured to be bonded to a wafer with an adhesive layer in the cavity of base such that the outer sidewall faces and is in contact with an edge of the wafer and the cavity faces a center of the wafer.

Abstract translation: 晶片载体包括具有设置在基部的中心处的空腔的基部和沿着基部的边缘延伸并远离基部的边缘的外侧壁以限定空腔。 空腔构造成填充有粘合剂层。 晶片载体构造成在基底的空腔中与粘合剂层结合到晶片，使得外侧壁面向并与晶片的边缘接触并且空腔面向晶片的中心。

公开(公告)号：US12081692B2

公开(公告)日：2024-09-03

申请号：US17980355

申请日：2022-11-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Shi-Yun Cho ,  Ji-Hyun Jung ,  Ho-Jin Lee ,  Young-Min Lee ,  Ho-Seong Seo ,  Youn-Ho Choi

IPC: H04M1/724 ,  G06F1/16 ,  G06F3/0488 ,  H04B1/3827

CPC classification number: H04M1/724 ,  G06F1/163 ,  G06F3/0488 ,  H04B1/385 ,  H04M2250/22

Abstract: A watch phone and a method for handling an incoming call using the watch phone are provided. In the watch phone, a display device includes a touch screen panel and a display, turns off the touch screen panel in a watch mode, turns on the touch screen panel in an idle mode or upon receipt of an incoming call, and displays at least two areas for call connection and call rejection, upon receipt of the incoming call. A single mode selection key selects one of the watch mode and the idle mode. A controller performs control operations so that the touch screen panel is turned off in the watch mode and is turned on in the idle mode or upon receipt of the incoming call, and connects or rejects the incoming call, when the at least two areas for call connection or call rejection, which are displayed upon receipt of the incoming call, are pointed to or dragged to.

公开(公告)号：US20220384311A1

公开(公告)日：2022-12-01

申请号：US17581084

申请日：2022-01-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seung Ha Oh ,  Kwang Jin Moon ,  Ho-Jin Lee

IPC: H01L23/48 ,  H01L21/768

Abstract: A semiconductor device comprises a substrate that including a frontside comprising an active region and a backside opposite to the frontside, an electronic element on the active region, a frontside wiring structure electrically connected to the electronic element on the frontside of the substrate, and a backside wiring structure electrically connected to the electronic element on the backside of the substrate. The backside wiring structure includes a plurality of backside wiring patterns sequentially stacked on the backside of the substrate, and a super via pattern that intersects and extends through at least one layer of the plurality of backside wiring patterns.