公开(公告)号：US11804472B2

公开(公告)日：2023-10-31

申请号：US17190113

申请日：2021-03-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hak-Seung Lee ,  Kwang-Jin Moon ,  Tae-Seong Kim ,  Dae-Suk Lee ,  Dong-Chan Lim

IPC: H01L25/065 ,  H01L23/31 ,  H01L23/48 ,  H01L23/522 ,  H01L23/528 ,  H01L23/00 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/5226 ,  H01L23/5283 ,  H01L24/09 ,  H01L24/17 ,  H01L25/50

Abstract: A semiconductor package includes a first semiconductor chip and a second semiconductor chip stacked on the first semiconductor chip. The first semiconductor chip includes a substrate having a first via hole, an insulation interlayer formed on the substrate and having a first bonding pad in an outer surface thereof and a second via hole connected to the first via hole and exposing the first bonding pad, and a plug structure formed within the first and second via holes to be connected to the first bonding pad. The second semiconductor chip includes a second bonding pad bonded to the plug structure which is exposed from a surface of the substrate of the first semiconductor chip.

公开(公告)号：US10978655B2

公开(公告)日：2021-04-13

申请号：US16562434

申请日：2019-09-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yi-Koan Hong ,  Kwang-Jin Moon ,  Nae-In Lee ,  Ho-Jin Lee

IPC: H01L23/485 ,  H01L51/44 ,  H01L25/065 ,  H01L23/532 ,  H01L23/538 ,  H01L23/00 ,  H01L51/00 ,  H01L21/768 ,  H01L25/00 ,  B82Y99/00 ,  B82Y10/00 ,  H01L25/18 ,  H01L27/146

Abstract: A semiconductor device includes a first conductive pattern at an upper portion of a first insulating interlayer on a first substrate, a first plurality of conductive nanotubes (CNTs) extending vertically, a second conductive pattern at a lower portion of a second insulating interlayer beneath a second substrate, and a second plurality of CNTs extending vertically. A lower surface of the second insulating interlayer contacts an upper surface of the first insulating interlayer. At least a portion of a sidewall of each of the first plurality of CNTs is covered by the first conductive pattern, and at least a portion of a sidewall of each of the second plurality of CNTs is covered by the second conductive pattern. The first and second conductive patterns vertically face each other, and at least one of the first plurality of CNTs and at least one of the second plurality of CNTs contact each other.

公开(公告)号：US10833032B2

公开(公告)日：2020-11-10

申请号：US16052383

申请日：2018-08-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seong-Min Son ,  Jeong-Gi Jin ,  Jin-Ho An ,  Jin-Ho Chun ,  Kwang-Jin Moon ,  Ho-Jin Lee

IPC: H01L23/00 ,  H01L23/485 ,  H01L23/522

Abstract: A semiconductor device includes a protective layer, a redistribution pattern, a pad pattern and an insulating polymer layer. The protective layer may be formed on a substrate. The redistribution pattern may be formed on the protective layer. An upper surface of the redistribution may be substantially flat. The pad pattern may be formed directly on the redistribution pattern. An upper surface of the pad pattern may be substantially flat. The insulating polymer layer may be formed on the redistribution pattern and the pad pattern. An upper surface of the insulating polymer layer may be lower than the upper surface of the pad pattern. The semiconductor device may have a high reliability.

公开(公告)号：US11043445B2

公开(公告)日：2021-06-22

申请号：US16386393

申请日：2019-04-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ju-Bin Seo ,  Su-Jeong Park ,  Tae-Seong Kim ,  Kwang-Jin Moon ,  Dong-Chan Lim ,  Ju-Il Choi

IPC: H01L23/48 ,  H01L23/31 ,  H01L23/522 ,  H01L23/532 ,  H01L21/768 ,  H01L27/146

Abstract: A semiconductor device is provided. The semiconductor device includes a first insulating interlayer disposed on a first surface of a substrate; a pad pattern disposed on a lower surface of the first insulating interlayer, the pad pattern including a first copper pattern; and a through silicon via passing through the substrate and the first insulating interlayer, and contacting the first copper pattern of the pad pattern. The through silicon via includes a first portion passing through the substrate and the first insulating interlayer, and a second portion under the first portion and extending to a portion of the first copper pattern in the pad pattern. A boundary of the through silicon via has a bent portion between the first portion and the second portion.

公开(公告)号：US10906283B2

公开(公告)日：2021-02-02

申请号：US16387032

申请日：2019-04-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Tae-Yeong Kim ,  Jun-Hyung Kim ,  Hoe-Chul Kim ,  Hoon-Joo Na ,  Kwang-Jin Moon

IPC: B32B37/00 ,  H01L21/687 ,  B32B37/10

Abstract: A wafer bonding apparatus including: a lower chuck to which a lower wafer is secured at a peripheral portion of the lower chuck; an upper chuck to which an upper wafer is secured; a bonding initiator for pressuring a central portion of the upper wafer until the central portion of the upper wafer reaches a central portion of the lower wafer, thereby initiating a bonding process of the upper and the lower wafers by deforming the upper wafer; and a bonding controller for controlling a bonding speed between a peripheral portion of the upper wafer and a peripheral portion of the lower wafer such that the upper wafer becomes un-deformed prior to bonding the peripheral portion of the upper wafer and the peripheral portion of the lower wafer.

公开(公告)号：US10446774B2

公开(公告)日：2019-10-15

申请号：US15870922

申请日：2018-01-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yi-Koan Hong ,  Kwang-Jin Moon ,  Nae-In Lee ,  Ho-Jin Lee

IPC: H01L23/48 ,  H01L51/44 ,  H01L25/065 ,  H01L23/532 ,  H01L23/538 ,  H01L21/768 ,  H01L51/00 ,  H01L23/00 ,  B82Y99/00 ,  B82Y10/00

Abstract: A semiconductor device includes a first conductive pattern at an upper portion of a first insulating interlayer on a first substrate, a first plurality of conductive nanotubes (CNTs) extending vertically, a second conductive pattern at a lower portion of a second insulating interlayer beneath a second substrate, and a second plurality of CNTs extending vertically. A lower surface of the second insulating interlayer contacts an upper surface of the first insulating interlayer. At least a portion of a sidewall of each of the first plurality of CNTs is covered by the first conductive pattern, and at least a portion of a sidewall of each of the second plurality of CNTs is covered by the second conductive pattern. The first and second conductive patterns vertically face each other, and at least one of the first plurality of CNTs and at least one of the second plurality of CNTs contact each other.

公开(公告)号：US09728490B2

公开(公告)日：2017-08-08

申请号：US15151079

申请日：2016-05-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ju-Il Choi ,  Hyo-Ju Kim ,  Yeun-Sang Park ,  Atsushi Fujisaki ,  Kwang-Jin Moon ,  Byung-Lyul Park

IPC: H01L23/485 ,  H01L23/48 ,  H01L23/31 ,  H01L23/532 ,  H01L23/29 ,  H01L23/528 ,  H01L23/522 ,  H01L23/00 ,  H01L21/768 ,  H01L23/498 ,  H01L21/48

CPC classification number: H01L23/481 ,  H01L21/486 ,  H01L21/76807 ,  H01L21/76898 ,  H01L23/291 ,  H01L23/3171 ,  H01L23/3192 ,  H01L23/49827 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/53271 ,  H01L23/5329 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/17 ,  H01L2224/03002 ,  H01L2224/0401 ,  H01L2224/05017 ,  H01L2224/05018 ,  H01L2224/05019 ,  H01L2224/05025 ,  H01L2224/05027 ,  H01L2224/05082 ,  H01L2224/05111 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05184 ,  H01L2224/05547 ,  H01L2224/05568 ,  H01L2224/05571 ,  H01L2224/05644 ,  H01L2224/06181 ,  H01L2224/13006 ,  H01L2224/131 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/1703 ,  H01L2224/17181 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01074 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/0496 ,  H01L2924/0501 ,  H01L2924/05032 ,  H01L2924/05042 ,  H01L2924/05442 ,  H01L2924/10252 ,  H01L2924/10253 ,  H01L2924/10271 ,  H01L2924/10328 ,  H01L2924/10329 ,  H01L2924/10331 ,  H01L2924/13091 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/014

Abstract: A semiconductor device includes a via structure penetrating through a substrate, a portion of the via structure being exposed over a surface of the substrate, a protection layer pattern structure provided on the surface of the substrate and including a first protection layer pattern and a second protection layer pattern, the first protection layer pattern surrounding a lower sidewall of the exposed portion of the via structure and exposing an upper sidewall of the exposed portion of the via structure, the second protection layer pattern exposing a portion of the top surface of the first protection layer pattern adjacent to the sidewall of the via structure, and a pad structure provided on the via structure and the protection layer pattern structure and covering the top surface of the first protection layer pattern exposed by the second protection layer pattern.

公开(公告)号：US09252141B2

公开(公告)日：2016-02-02

申请号：US14326282

申请日：2014-07-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kwang-Jin Moon ,  Byung-Lyul Park ,  Jae-Hwa Park

IPC: H01L27/02 ,  H01L23/48 ,  H01L27/088

CPC classification number: H01L27/0296 ,  H01L21/76898 ,  H01L23/481 ,  H01L27/088 ,  H01L2224/16225 ,  H01L2924/15311

Abstract: A semiconductor integrated circuit device includes a TSV (Through Silicon Via) extending through a substrate, a first well in the substrate adjacent a first surface of the substrate, a gate of an active device on the first well, a charging protection well, and a charging protection gate on the charging protection well. The charging protection well is disposed in the substrate adjacent the first surface of the substrate, is interposed between the TSV hole and the first well, and surrounds the TSV hole. The charging protection gate prevents the gate of the active device from being damaged when the TSV is formed especially when using a plasma etch process to form a TSV hole in the substrate.

Abstract translation: 半导体集成电路器件包括延伸穿过衬底的TSV（贯通硅通孔），邻近衬底第一表面的衬底中的第一阱，第一阱上的有源器件的栅极，充电保护阱和 充电保护门对充电保护良好。 充电保护孔设置在基板的与基板的第一表面相邻的基板中，插入在TSV孔和第一阱之间，并且包围TSV孔。 当TSV形成时，充电保护门防止有源器件的栅极被损坏，特别是当使用等离子体蚀刻工艺在衬底中形成TSV孔时。

公开(公告)号：US12014972B2

公开(公告)日：2024-06-18

申请号：US17403154

申请日：2021-08-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ju-Il Choi ,  Kwang-Jin Moon ,  Byung-Lyul Park ,  Jin-Ho An ,  Atsushi Fujisaki

IPC: H01L23/48 ,  H01L21/768 ,  H01L23/00 ,  H01L23/532 ,  H01L25/065 ,  H01L25/18

CPC classification number: H01L23/481 ,  H01L21/76898 ,  H01L24/03 ,  H01L24/05 ,  H01L24/14 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/5329 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/03618 ,  H01L2224/0401 ,  H01L2224/05018 ,  H01L2224/05025 ,  H01L2224/05027 ,  H01L2224/05155 ,  H01L2224/05546 ,  H01L2224/05557 ,  H01L2224/05558 ,  H01L2224/05559 ,  H01L2224/05564 ,  H01L2224/05567 ,  H01L2224/05568 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05572 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05684 ,  H01L2224/06181 ,  H01L2224/10 ,  H01L2224/13023 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/16013 ,  H01L2224/16111 ,  H01L2224/16112 ,  H01L2224/16113 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16147 ,  H01L2224/16148 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/15311 ,  H01L2224/73204 ,  H01L2224/16145 ,  H01L2224/32145 ,  H01L2924/00 ,  H01L2224/05655 ,  H01L2924/00014 ,  H01L2224/05647 ,  H01L2924/00014 ,  H01L2224/05684 ,  H01L2924/00014 ,  H01L2224/05624 ,  H01L2924/00014 ,  H01L2224/05611 ,  H01L2924/013 ,  H01L2924/01047 ,  H01L2224/03618 ,  H01L2924/00014 ,  H01L2224/13139 ,  H01L2924/00014 ,  H01L2224/13147 ,  H01L2924/00014

Abstract: A method of manufacturing a semiconductor device is provided. The method includes forming a preliminary via structure through a portion of a substrate; partially removing the substrate to expose a portion of the preliminary via structure; forming a protection layer structure on the substrate to cover the portion of the preliminary via structure that is exposed; partially etching the protection layer structure to form a protection layer pattern structure and to partially expose the preliminary via structure; wet etching the preliminary via structure to form a via structure; and forming a pad structure on the via structure to have a flat top surface.

公开(公告)号：US11469202B2

公开(公告)日：2022-10-11

申请号：US17029639

申请日：2020-09-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seong-Min Son ,  Jeong-Gi Jin ,  Jin-Ho An ,  Jin-Ho Chun ,  Kwang-Jin Moon ,  Ho-Jin Lee

IPC: H01L23/00 ,  H01L23/485 ,  H01L23/522

Abstract: A semiconductor device includes a protective layer, a redistribution pattern, a pad pattern and an insulating polymer layer. The protective layer may be formed on a substrate. The redistribution pattern may be formed on the protective layer. An upper surface of the redistribution may be substantially flat. The pad pattern may be formed directly on the redistribution pattern. An upper surface of the pad pattern may be substantially flat. The insulating polymer layer may be formed on the redistribution pattern and the pad pattern. An upper surface of the insulating polymer layer may be lower than the upper surface of the pad pattern.