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公开(公告)号：US20220352204A1
公开(公告)日：2022-11-03
申请号：US17860618
申请日：2022-07-08
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Kyunghwa YUN , Chanho Kim , Dongku Kang
IPC: H01L27/11582 , H01L27/11565 , H01L27/11556 , H01L27/11519 , H01L27/11526 , H01L27/11573
Abstract: A nonvolatile memory device includes a peripheral circuit including a first active region and a memory block including a second active region on the peripheral circuit. The memory block includes a vertical structure including pairs of a first insulating layer and a first conductive layer, a second insulating layer on the vertical structure, a second conductive layer and a third conductive layer spaced apart from each other on the second insulating layer, first vertical channels and second vertical channels. The second conductive layer and the third conductive layer are connected with a first through via penetrating the vertical structure, the second active region, and a region of the second insulating layer that is exposed between the second conductive layer and the third conductive layer.
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公开(公告)号：US11329057B2
公开(公告)日：2022-05-10
申请号：US16944733
申请日：2020-07-31
Applicant: Samsung Electronics Co., Ltd.
Inventor： Chanho Kim , Dongku Kang , Daeseok Byeon
IPC: H01L23/48 , H01L23/52 , H01L29/40 , H01L27/112 , H01L27/11585 , H01L27/108 , H01L27/24
Abstract: An integrated circuit device includes a memory including a memory cell insulation surrounding a memory stack and a memory cell interconnection unit, a peripheral circuit including a peripheral circuit region formed on a peripheral circuit board, and a peripheral circuit interconnection between the peripheral circuit region and the memory structure, a plurality of conductive bonding structures on a boundary between the memory cell interconnection and the peripheral circuit interconnection in a first region, the first region overlapping the memory stack in a vertical direction, and a through electrode penetrating one of the memory cell insulation and the peripheral circuit board and extended to a lower conductive pattern included in the peripheral circuit interconnection in a second region, the second region overlapping the memory cell insulation in the vertical direction.
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公开(公告)号：US11289500B2
公开(公告)日：2022-03-29
申请号：US17001035
申请日：2020-08-24
Applicant: Samsung Electronics Co., Ltd.
Inventor： Kyunghwa Yun , Pansuk Kwak , Chanho Kim , Dongku Kang
IPC: G11C16/04 , H01L27/11573 , H01L27/1157 , G11C16/08 , G11C7/18 , H01L27/11524 , H01L27/11519 , H01L27/11529 , H01L27/11556 , H01L27/11565 , H01L27/11582
Abstract: A memory device comprises a peripheral circuit region including a first substrate and circuit elements on the first substrate, the circuit elements including a row decoder, and a memory cell region including a cell array region and a cell contact region, wherein the cell array region includes wordlines, stacked on a second substrate on the peripheral circuit region, and channel structures extending in a direction perpendicular to an upper surface of the second substrate and penetrating the wordlines, wherein the cell contact region includes cell contacts connected to the wordlines and on both sides of the cell array region in a first direction parallel to the upper surface of the second substrate, the cell contacts including a first cell contact region and a second cell contact region, the first and second cell contact regions having different lengths to each other in the first direction, wherein each of the first and second cell contact regions includes first pads having different lengths than each other in the first direction, and second pads different from the first pads, wherein the cell contacts are connected to the wordlines in the first pads, wherein the number of the second pads included in the first cell contact region is greater than the number of the second pads included in the second cell contact region, and wherein the memory cell region includes a first metal pad and the peripheral circuit region includes a second metal pad, and the memory cell region and the peripheral circuit region are vertically connected to each other by the first metal pad and the second metal pad.
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公开(公告)号：US11282827B2
公开(公告)日：2022-03-22
申请号：US16940333
申请日：2020-07-27
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Kyunghwa Yun , Chanho Kim , Dongku Kang
IPC: H01L25/18 , H01L23/00 , H01L25/065 , H01L27/11519 , H01L27/11565 , H01L27/11582 , H01L25/00 , H01L27/11548 , H01L27/11575 , H01L27/11556
Abstract: A nonvolatile memory device includes a memory cell region including first metal pads, and a peripheral circuit region including second metal pads. The memory cell region includes a vertical structure including pairs of a first insulating layer and a first conductive layer, a second insulating layer on the vertical structure, a second conductive layer and a third conductive layer spaced apart from each other on the second insulating layer, first vertical channels and second vertical channels. The second conductive layer and the third conductive layer are connected with a first through via penetrating the vertical structure and a region of the second insulating layer that is exposed between the second conductive layer and the third conductive layer. The peripheral circuit region is vertically connected to the memory cell region by the first metal pads and the second metal pads directly.
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公开(公告)号：US12211830B2
公开(公告)日：2025-01-28
申请号：US18179056
申请日：2023-03-06
Applicant: Samsung Electronics Co., Ltd.
Inventor： Chanho Kim , Dongku Kang , Daeseok Byeon
Abstract: An integrated circuit device includes a memory including a memory cell insulation surrounding a memory stack and a memory cell interconnection unit, a peripheral circuit including a peripheral circuit region formed on a peripheral circuit board, and a peripheral circuit interconnection between the peripheral circuit region and the memory structure, a plurality of conductive bonding structures on a boundary between the memory cell interconnection and the peripheral circuit interconnection in a first region, the first region overlapping the memory stack in a vertical direction, and a through electrode penetrating one of the memory cell insulation and the peripheral circuit board and extended to a lower conductive pattern included in the peripheral circuit interconnection in a second region, the second region overlapping the memory cell insulation in the vertical direction.
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Patent Agency Ranking
公开(公告)号：US11675392B2
公开(公告)日：2023-06-13
申请号：US17564773
申请日：2021-12-29
Applicant: Samsung Electronics Co., Ltd.
Inventor： Jinyong Park , Dongku Kang , Jichul Kim , Bongkyu Min , Baekeun Cho , Chihyun Cho , Hyuncheol Jin
CPC classification number: G06F1/1652 , G06F1/1624 , G06F1/1635 , G06F1/1698 , G06F1/183
Abstract: An electronic device is provided. The electronic device includes a rollable display. The electronic device may include a main bracket configured to support the first portion of the rollable display, a roller member disposed in the first direction from the main bracket and arranged in a third direction perpendicular to the first direction, at least one folding support member disposed between the main bracket and the roller member and configured to support the second portion of the rollable display, a circuit board disposed to overlap at least a portion of the main bracket, at least one electronic component disposed adjacent to the roller member, and a FPCB configured to electrically connecting the main circuit board and the electronic component, wherein the FPCB is disposed to pass through the folding support member and extends from a portion of the circuit board to a portion of the electronic component.
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公开(公告)号：US11651829B2
公开(公告)日：2023-05-16
申请号：US16941956
申请日：2020-07-29
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Kyung-Min Kang , Dongku Kang , Su Chang Jeon , Won-Taeck Jung
CPC classification number: G11C16/3481 , G11C16/08 , G11C16/10 , G11C16/28 , G11C16/30
Abstract: A nonvolatile memory device includes a peripheral circuit region and a memory cell region vertically connected with the peripheral circuit region, the peripheral circuit region including at least one first metal pad, and the memory cell region including at least one second metal pad directly connected with the at least one first metal pad. A method of programming the nonvolatile memory device includes: receiving a programming command, data for a plurality of pages, and an address corresponding to a selected word-line; programming the data for one of the pages to an unselected word-line; reading data of a previously programmed page from the selected word-line; and programming the data for the remaining pages and the data of the previously programmed page to the selected word-line.
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公开(公告)号：US11632881B2
公开(公告)日：2023-04-18
申请号：US16952595
申请日：2020-11-19
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Chihwan Jeong , Kyungha Koo , Jihong Kim , Dongku Kang , Kuntak Kim , Yunjeong Park , Kyuhwan Lee , Haejin Lee , Seyoung Jang , Hyuntae Jang
Abstract: The disclosure relates to a wireless charging device including a cooling fan, and the wireless charging device according to an embodiment of the disclosure includes: a housing including a holding portion configured to hold an external electronic device; a first bracket positioned in the holding portion; a conductive coil disposed in the first bracket; a second bracket positioned in the holding portion and including a penetrating hole; a first cooling fan positioned in the penetrating hole; a second cooling fan positioned in the penetrating hole and spaced apart from the first cooling fan; and a partition formed in the penetrating hole to isolate the first cooling fan and the second cooling fan from each other, the penetrating hole being divided into a first area having the first cooling fan disposed therein and a second area having the second cooling fan positioned therein, at least one protrusion having a volute shape formed on at least a portion of the second bracket or at least a portion of the partition, a first opening formed on at least an area of the first bracket to allow air cooled by the first cooling fan and/or the second cooling fan to move to the holding portion, and a second opening formed on at least an area of the holding portion to allow the air transmitted from the first opening to move outside the wireless charging device.
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公开(公告)号：US11456317B2
公开(公告)日：2022-09-27
申请号：US17023053
申请日：2020-09-16
Applicant: Samsung Electronics Co., Ltd.
Inventor： Chanho Kim , Daeseok Byeon , Dongku Kang
IPC: H01L27/11573 , H01L27/11582 , G11C8/14 , H01L23/522 , H01L23/528 , H01L27/11526 , H01L27/11519 , H01L27/11556 , H01L27/11565
Abstract: A memory device includes a peripheral circuit region comprising a first substrate, a plurality of metal layers over the first substrate, and a first metal pad, a cell region comprising a second substrate, a plurality of gate lines over the second substrate, a plurality of upper interconnection layers in the second substrate, and a second metal pad, wherein the cell region is vertically connected to the peripheral circuit region by the first metal pad and the second metal pad, a common source line between the second substrate and the plurality of gate lines, the common source line comprising a through hole, and a word line cut region extending across the plurality of gate lines and extending through the through hole of the common source line to be connected to a first upper interconnection layer from among the plurality of upper interconnection layers.
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公开(公告)号：US09633704B2
公开(公告)日：2017-04-25
申请号：US15188461
申请日：2016-06-21
Applicant: Samsung Electronics Co., Ltd.
Inventor： Dongku Kang
CPC classification number: G11C7/12 , G11C7/065 , G11C16/10 , G11C16/24 , G11C16/3459
Abstract: A program method of a nonvolatile memory device includes loading first word line data to be stored in first memory cells connected to a first word line and second word line data to be stored in second memory cells connected to a second word line; setting up upper bit lines according to the first word line data; turning off bit line sharing transistors after the upper bit lines are set up; setting up lower bit lines according to the second word line data; performing a first program operation on the first memory cells using the upper bit lines; turning on the bit line sharing transistors; and performing a second program operation on the second memory cells using the lower bit lines. The bit line sharing transistors electrically connect the upper bit lines and the lower bit lines in response to a bit line sharing signal.
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