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公开(公告)号：US11675392B2
公开(公告)日：2023-06-13
申请号：US17564773
申请日：2021-12-29
发明人： Jinyong Park , Dongku Kang , Jichul Kim , Bongkyu Min , Baekeun Cho , Chihyun Cho , Hyuncheol Jin
CPC分类号： G06F1/1652 , G06F1/1624 , G06F1/1635 , G06F1/1698 , G06F1/183
摘要： An electronic device is provided. The electronic device includes a rollable display. The electronic device may include a main bracket configured to support the first portion of the rollable display, a roller member disposed in the first direction from the main bracket and arranged in a third direction perpendicular to the first direction, at least one folding support member disposed between the main bracket and the roller member and configured to support the second portion of the rollable display, a circuit board disposed to overlap at least a portion of the main bracket, at least one electronic component disposed adjacent to the roller member, and a FPCB configured to electrically connecting the main circuit board and the electronic component, wherein the FPCB is disposed to pass through the folding support member and extends from a portion of the circuit board to a portion of the electronic component.
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公开(公告)号：US20180269126A1
公开(公告)日：2018-09-20
申请号：US15983125
申请日：2018-05-18
发明人： Yunhyeok Im , Oleg Feygenson , Sang Il Kim , Youngbae Kim , Jichul Kim , Seungkon Mok , Jungsu Ha
IPC分类号： H01L23/367 , H01L23/373 , H01L25/00 , H01L23/552 , H01L23/00 , H01L29/06 , H01L21/56 , H01L25/10 , H01L23/498
CPC分类号： H01L23/367 , H01L21/4871 , H01L21/563 , H01L23/36 , H01L23/3736 , H01L23/49816 , H01L23/552 , H01L23/562 , H01L24/13 , H01L24/16 , H01L24/32 , H01L24/48 , H01L24/73 , H01L24/92 , H01L25/105 , H01L25/50 , H01L29/0657 , H01L2224/13025 , H01L2224/16225 , H01L2224/16227 , H01L2224/32225 , H01L2224/45099 , H01L2224/48091 , H01L2224/48227 , H01L2224/73204 , H01L2224/73253 , H01L2224/73265 , H01L2224/92125 , H01L2225/1023 , H01L2225/1058 , H01L2225/1094 , H01L2924/00014 , H01L2924/10158 , H01L2924/15311 , H01L2924/15331 , H01L2924/181 , H01L2924/18161 , H01L2924/3025 , H01L2924/3511 , H01L2924/00012 , H01L2924/00
摘要： Semiconductor packages and methods of fabricating the same are disclosed. The semiconductor package may include a package substrate, a semiconductor chip, which is mounted on the package substrate to have a bottom surface facing the package substrate and a top surface opposite to the bottom surface, a mold layer provided on the package substrate to encapsulate the semiconductor chip, and a heat dissipation layer provided on the top surface of the semiconductor chip. The mold layer may have a top surface substantially coplanar with the top surface of the semiconductor chip, and the top surfaces of the semiconductor chip and the mold layer may have a difference in surface roughness from each other.
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公开(公告)号：US10347611B2
公开(公告)日：2019-07-09
申请号：US15406925
申请日：2017-01-16
发明人： Jichul Kim , Jae Choon Kim , Hansung Ryu , KyongSoon Cho , YoungSang Cho , Yeo-Hoon Yoon
IPC分类号： H01L23/48 , H01L25/10 , H01L21/48 , H01L21/56 , H01L23/538 , H01L23/00 , H01L25/00 , H01L23/498 , H01L29/06
摘要： A semiconductor package is provided which includes a redistribution substrate, an interconnect substrate on the redistribution substrate, a metal layer on the semiconductor chip, a semiconductor chip on the redistribution substrate and in the hole of the interconnect substrate, and a mold layer in a gap between the semiconductor chip and the interconnect substrate. The interconnect substrate includes a hole penetrating thereinside. The interconnect substrate includes base layers and a conductive member extending through the base layers. A top surface of the interconnect substrate is positioned either above or below the level of the top surface of the metal layer.
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公开(公告)号：US09651431B2
公开(公告)日：2017-05-16
申请号：US14136787
申请日：2013-12-20
发明人： Jae Choon Kim , Jichul Kim , Jin-Kwon Bae , Eunho Jung
CPC分类号： G01K7/42 , G01K3/06 , H01L2224/16225 , H01L2224/48091 , H01L2224/73265 , H01L2924/15311 , H01L2924/00014
摘要： A semiconductor package includes a first package including a first substrate and a first semiconductor chip mounted on the first substrate and a second package facing and spaced apart from the first package. The second package includes a second substrate on which a second semiconductor chip is mounted. The semiconductor package also includes a connection structure electrically connecting the first and second packages to each other, a first temperature sensor connected to the first substrate, a second temperature sensor connected to the first semiconductor chip, and a third temperature sensor connected to the second semiconductor chip.
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公开(公告)号：US11832389B2
公开(公告)日：2023-11-28
申请号：US17431900
申请日：2021-08-13
发明人： Taewon Sun , Jichul Kim , Kicheol Bae , Jinyong Park , Jungje Bang , Yongjae Song
CPC分类号： H05K1/14 , H04M1/0249 , H05K1/0216 , H05K1/181 , H05K7/1427 , H05K2201/10378
摘要： An electronic device according to various embodiments may include: a display, a first circuit board disposed under the display, a first component and a second component disposed on one surface of the first circuit board, the first and second components each having different heights, a first interposer surrounding at least one side surface of the first component and disposed in a first region of the first circuit board, the first interposer part having a first height, a second interposer part surrounding at least one side surface of the second component and disposed in a second region of the first circuit board, the second interposer part having a second height different from the first height, a first second circuit board, at least a portion of which is spaced apart from the first region of the first circuit board, the first second circuit board including a first first portion bonded to the first interposer part, and a second second circuit board, at least a portion of which is spaced apart from the second region of the first circuit board, the second second circuit board including a first second portion bonded to the second interposer and spaced apart from the first second circuit board by a specified gap.
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公开(公告)号：US10937771B2
公开(公告)日：2021-03-02
申请号：US16430428
申请日：2019-06-04
发明人： Jichul Kim , Jae Choon Kim , Hansung Ryu , KyongSoon Cho , YoungSang Cho , Yeo-Hoon Yoon
IPC分类号： H01L23/48 , H01L25/10 , H01L21/48 , H01L21/56 , H01L23/538 , H01L23/00 , H01L25/00 , H01L21/683 , H01L23/498 , H01L29/06
摘要： A semiconductor package is provided which includes a redistribution substrate, an interconnect substrate on the redistribution substrate, a metal layer on the semiconductor chip, a semiconductor chip on the redistribution substrate and in the hole of the interconnect substrate, and a mold layer in a gap between the semiconductor chip and the interconnect substrate. The interconnect substrate includes a hole penetrating thereinside. The interconnect substrate includes base layers and a conductive member extending through the base layers. A top surface of the interconnect substrate is positioned either above or below the level of the top surface of the metal layer.
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公开(公告)号：US10510737B2
公开(公告)日：2019-12-17
申请号：US15786698
申请日：2017-10-18
发明人： Jichul Kim , Chajea Jo , Sang-Uk Han , Kyoung Soon Cho , Jae Choon Kim , Woohyun Park
IPC分类号： H01L25/18 , H01L27/146 , H01L23/00 , H01L25/00 , H01L23/367 , H01L23/18
摘要： A semiconductor package includes a first semiconductor chip on a substrate, a second semiconductor chip on the substrate and spaced apart from the first semiconductor device, a mold layer on the substrate and covering sides of the first and second semiconductor chips, and an image sensor unit on the first and second semiconductor chips and the mold layer. The image sensor unit is electrically connected to the first semiconductor chip.
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公开(公告)号：US09903764B2
公开(公告)日：2018-02-27
申请号：US14617097
申请日：2015-02-09
发明人： Kyungsoo Lee , Sridhar Sundaram , Wook Kim , Jichul Kim , MyungKyoon Yim
CPC分类号： G01K1/026 , G01K7/425 , G01R21/02 , G06F1/26 , G06F17/5036 , G06F2217/80
摘要： A power estimation circuit including: a power estimation manager circuit configured to receive power data and temperature data; and a storage circuit that includes a first region storing resistive-capacitive (RC) thermal modeling data, a second region storing the power data and a third region storing the temperature data, wherein the power estimation manager circuit is configured to estimate power consumption of a first node at a second time point, which occurs after a first time point, using the RC thermal modeling data, the power data and the temperature data.
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公开(公告)号：US09679874B2
公开(公告)日：2017-06-13
申请号：US14938788
申请日：2015-11-11
发明人： Jin-Kwon Bae , Jae Choon Kim , Jichul Kim , Kyol Park , Chajea Jo
IPC分类号： H01L23/31 , H01L23/498 , H01L23/367 , H01L25/065 , H01L23/00 , H01L23/36 , H01L23/538
CPC分类号： H01L25/0657 , H01L23/36 , H01L23/367 , H01L23/49816 , H01L23/49827 , H01L23/5385 , H01L24/00 , H01L24/29 , H01L24/32 , H01L25/0655 , H01L2224/16145 , H01L2224/16146 , H01L2224/16225 , H01L2224/17181 , H01L2224/29011 , H01L2224/3205 , H01L2224/32145 , H01L2224/32225 , H01L2224/73204 , H01L2224/73253 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06555 , H01L2225/06589 , H01L2924/1431 , H01L2924/1432 , H01L2924/1434 , H01L2924/15192 , H01L2924/15311 , H01L2924/00
摘要： A semiconductor device includes a substrate, a first semiconductor package disposed on the substrate, and a second semiconductor package spaced apart from the first semiconductor package on the substrate. The second semiconductor package includes a semiconductor chip stacked on the substrate, an adhesion part covering the semiconductor chip, and a heat-blocking structure disposed between the substrate and the semiconductor chip. Heat generated from the first semiconductor package and transmitted to the second semiconductor package through the substrate is blocked by the heat-blocking structure.
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公开(公告)号：US09671141B2
公开(公告)日：2017-06-06
申请号：US14961167
申请日：2015-12-07
发明人： Jae Choon Kim , Jichul Kim , Jin-Kwon Bae , Eunseok Cho
CPC分类号： F25B21/02 , F25B2321/0212 , F25B2700/2107 , H01L35/32 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2924/12044 , H01L2924/00014 , H01L2924/00
摘要： A device includes a first board having a first area and a second area not overlapping the first area; and a thermoelectric semiconductor disposed between the first board and the second board at the first area of the first board configured to supply a voltage to the thermoelectric semiconductor; a package disposed at the second area of the first board.
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