公开(公告)号：US11380606B2

公开(公告)日：2022-07-05

申请号：US16932726

申请日：2020-07-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Eunji Kim ,  Sungdong Cho ,  Kwangwuk Park ,  Sangjun Park ,  Daesuk Lee ,  Hakseung Lee

IPC: H01L23/48 ,  H01L21/768 ,  H01L25/18 ,  H01L23/528 ,  H01L23/498 ,  H01L23/522 ,  H01L21/3065

Abstract: A semiconductor device includes a semiconductor substrate having an active surface on which semiconductor elements are provided. An interlayer insulating film is provided on the semiconductor substrate. A first via structure passes through the semiconductor substrate. The first via structure has a first diameter. A second via structure passes through the semiconductor substrate. The second via structure has a second diameter that is greater than the first diameter. The first via structure has a step portion that is in contact with the interlayer insulating film.

公开(公告)号：US20210020543A1

公开(公告)日：2021-01-21

申请号：US16794782

申请日：2020-02-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hakseung Lee ,  Jinnam Kim ,  Kwangjin Moon ,  Eunji Kim ,  Taeseong Kim ,  Sangjun Park

IPC: H01L23/48 ,  H01L25/18 ,  H01L21/768 ,  H01L23/00

Abstract: A semiconductor device includes a semiconductor substrate including at least one semiconductor structure, an interlayer insulating layer disposed on the semiconductor substrate, at least one first via structure penetrating the semiconductor substrate and the interlayer insulating layer, including a first region having a first width at an upper surface of the interlayer insulating layer and a second region extending from the first region and having a second width at a lower surface of the semiconductor substrate, wherein a side surface of the first region and a side surface of the second region have different profiles at a boundary between the first region and the second region, and at least one second via structure penetrating the semiconductor substrate and the interlayer insulating layer and having a third width greater than the first width at an upper surface of the interlayer insulating layer.

公开(公告)号：US11791137B2

公开(公告)日：2023-10-17

申请号：US16855048

申请日：2020-04-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hakseung Lee ,  Ho-Jin Lee ,  Dong-Chan Lim ,  Jinnam Kim ,  Kwangjin Moon

IPC: H01J37/32 ,  H01L21/67

CPC classification number: H01J37/32642 ,  H01J37/32715 ,  H01L21/67069 ,  H01J2237/334

Abstract: A bevel etching apparatus includes a chuck plate that is configured to receive a substrate, a lower ring surrounding a circumference of the chuck plate, a cover plate on the chuck plate, and an upper ring surrounding a circumference of the cover plate. The lower ring includes a ring base and a protrusion that extends upwardly from an edge of the ring base and surrounds a lower portion of a sidewall of the substrate.

公开(公告)号：US11373932B2

公开(公告)日：2022-06-28

申请号：US16750579

申请日：2020-01-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyoukyung Cho ,  Daesuk Lee ,  Jinnam Kim ,  Taeseong Kim ,  Kwangjin Moon ,  Hakseung Lee

IPC: H01L23/48 ,  H01L23/00 ,  H01L25/065 ,  H01L23/532 ,  H01L21/768 ,  H01L21/02 ,  H01L21/306 ,  H01L23/528 ,  H01L21/027 ,  H01L21/288 ,  H01L21/321

Abstract: Disclosed are semiconductor packages and methods of fabricating the same. The semiconductor package comprises a first wiring layer, a first semiconductor substrate on the first wiring layer, a first dielectric layer on the first semiconductor substrate, a landing pad in the first wiring layer, a through hole that penetrates the first semiconductor substrate, the first dielectric layer, and the first wiring layer and exposes the landing pad, the through hole including a first hole and a second hole on a bottom end of the first hole, the second hole having a maximum diameter less than a minimum diameter of the first hole, and a mask layer on an upper lateral surface of the through hole.

公开(公告)号：US11133240B2

公开(公告)日：2021-09-28

申请号：US16794782

申请日：2020-02-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hakseung Lee ,  Jinnam Kim ,  Kwangjin Moon ,  Eunji Kim ,  Taeseong Kim ,  Sangjun Park

IPC: H01L23/48 ,  H01L25/18 ,  H01L21/768 ,  H01L25/065 ,  H01L23/00

Abstract: A semiconductor device includes a semiconductor substrate including at least one semiconductor structure, an interlayer insulating layer disposed on the semiconductor substrate, at least one first via structure penetrating the semiconductor substrate and the interlayer insulating layer, including a first region having a first width at an upper surface of the interlayer insulating layer and a second region extending from the first region and having a second width at a lower surface of the semiconductor substrate, wherein a side surface of the first region and a side surface of the second region have different profiles at a boundary between the first region and the second region, and at least one second via structure penetrating the semiconductor substrate and the interlayer insulating layer and having a third width greater than the first width at an upper surface of the interlayer insulating layer.

公开(公告)号：US20210066386A1

公开(公告)日：2021-03-04

申请号：US16855048

申请日：2020-04-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hakseung Lee ,  Ho-Jin Lee ,  Dong-Chan Lim ,  Jinnam Kim ,  Kwangjin Moon

IPC: H01L27/146 ,  H01L21/67 ,  H01J37/32

Abstract: A bevel etching apparatus includes a chuck plate that is configured to receive a substrate, a lower ring surrounding a circumference of the chuck plate, a cover plate on the chuck plate, and an upper ring surrounding a circumference of the cover plate. The lower ring includes a ring base and a protrusion that extends upwardly from an edge of the ring base and surrounds a lower portion of a sidewall of the substrate.

公开(公告)号：US20210043575A1

公开(公告)日：2021-02-11

申请号：US16849085

申请日：2020-04-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hakseung Lee ,  Jinnam Kim ,  Hyoukyung Cho ,  Taeseong Kim ,  Kwangjin Moon

IPC: H01L23/538

Abstract: A semiconductor device may include a first semiconductor substrate having a first surface and a second surface opposite to each other, a first circuit layer provided on the first surface of the first semiconductor substrate, a connection pad provided on the second surface of the first semiconductor substrate, and a first penetration via and a second penetration via penetrating the first semiconductor substrate and at least a portion of the first circuit layer. The first penetration via and the second penetration via may be provided in a first penetration hole and a second penetration hole, respectively. Each of the first and second penetration holes may include a first portion, a second portion, and a third portion. A width of the first portion of the first penetration hole may be smaller than a width of the first portion of the second penetration hole.