公开(公告)号：US10319814B2

公开(公告)日：2019-06-11

申请号：US15467159

申请日：2017-03-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Shigenobu Maeda ,  Hee-Soo Kang ,  Sang-Pil Sim ,  Soo-Hun Hong

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/417 ,  H01L29/66 ,  B82Y10/00 ,  H01L27/12 ,  H01L27/088 ,  H01L29/10 ,  H01L21/8234 ,  H01L21/84 ,  H01L29/08 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/49 ,  H01L29/51 ,  H01L29/775

Abstract: A semiconductor device can include a field insulation layer including a planar major surface extending in first and second orthogonal directions and a protruding portion that protrudes a particular distance from the major surface relative to the first and second orthogonal directions. First and second multi-channel active fins can extend on the field insulation layer, and can be separated from one another by the protruding portion. A conductive layer can extend from an uppermost surface of the protruding portion to cross over the protruding portion between the first and second multi-channel active fins.

公开(公告)号：US09755074B2

公开(公告)日：2017-09-05

申请号：US14953769

申请日：2015-11-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jae-Yup Chung ,  Hee-Soo Kang ,  Hee-Don Jeong ,  Se-Wan Park

IPC: H01L29/78 ,  H01L27/088

CPC classification number: H01L29/7848 ,  H01L27/0886 ,  H01L29/785

Abstract: A semiconductor device includes a first multi-channel active pattern, a field insulation layer disposed on the first multi-channel active pattern and including a first region and a second region, the first region having a top surface protruding from a top surface of the second region to a top surface of the first multi-channel active pattern, a first gate electrode crossing the first multi-channel active pattern, the first gate electrode being disposed on the field insulation layer, and a first source or drain disposed between the first gate electrode and the first region of the field insulation layer and including a first facet, the first facet being disposed adjacent to the first region of the field insulation layer at a point lower than the top surface of the first multi-channel active pattern.

公开(公告)号：US09379106B2

公开(公告)日：2016-06-28

申请号：US14504822

申请日：2014-10-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Soo-Hun Hong ,  Hee-Soo Kang ,  Hyun-Jo Kim ,  Sang-Pil Sim ,  Hee-Don Jung

IPC: H01L29/06 ,  H01L27/088 ,  H01L21/8234

CPC classification number: H01L29/66545 ,  H01L21/762 ,  H01L21/76229 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823431 ,  H01L21/823481 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: A semiconductor device includes a substrate including first to third fins aligned in a first direction, a first trench arranged between the first fin and the second fin, and a second trench arranged between the second fin and the third fin. The semiconductor device further includes a first field insulating film arranged in the first trench, a second field insulating film formed in the second trench, a first dummy gate arranged on the first field insulating film, and a second dummy gate at least partly arranged on the second field insulating film. A lower surface of the second field insulating film is arranged to be lower than a lower surface of the first field insulating film.

Abstract translation: 一种半导体器件包括：衬底，包括沿第一方向排列的第一至第三鳍片，布置在第一鳍片和第二鳍片之间的第一沟槽，以及布置在第二鳍片和第三鳍片之间的第二沟槽。 半导体器件还包括布置在第一沟槽中的第一场绝缘膜，形成在第二沟槽中的第二场绝缘膜，布置在第一场绝缘膜上的第一虚栅极，以及至少部分地布置在第二沟槽上的第二虚栅极 第二场绝缘膜。 第二场绝缘膜的下表面被布置成低于第一场绝缘膜的下表面。

公开(公告)号：US20140353763A1

公开(公告)日：2014-12-04

申请号：US14287322

申请日：2014-05-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae-Yup Chung ,  Hee-Soo Kang ,  Soo-Hun Hong

IPC: H01L27/088

CPC classification number: H01L27/0886 ,  H01L21/823431

Abstract: Semiconductor devices including fin-FETs and methods of forming the semiconductor devices are provided. The semiconductor devices may include a fin structure including a long side and a short side on a substrate, a first trench including a sidewall defined by the long side of the fin structure and a first field insulating layer in the first trench. The semiconductor devices may also include a second trench including a sidewall defined by the short side of the fin structure and a second field insulating layer in the second trench. A first distance between an uppermost surface of the fin structure and a lowermost surface of the first trench may be different from a second distance between the uppermost surface of the fin structure and a lowermost surface of the second trench.

Abstract translation: 提供了包括鳍式FET的半导体器件和形成半导体器件的方法。 半导体器件可以包括在衬底上包括长边和短边的鳍结构，包括由鳍结构的长边限定的侧壁的第一沟槽和在第一沟槽中的第一场绝缘层。 半导体器件还可以包括第二沟槽，其包括由鳍结构的短边限定的侧壁和在第二沟槽中的第二场绝缘层。 翅片结构的最上表面和第一沟槽的最下表面之间的第一距离可以不同于翅片结构的最上表面和第二沟槽的最下表面之间的第二距离。

公开(公告)号：US20140225198A1

公开(公告)日：2014-08-14

申请号：US13829703

申请日：2013-03-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sung-Dae Suk ,  Hee-Soo Kang ,  Sung-Il Park ,  Sang-Hoon Lee

IPC: H01L27/092 ,  H01L21/8238

CPC classification number: H01L27/0922 ,  H01L21/823871

Abstract: A semiconductor device includes a substrate having a first region and a second region, first and second gate electrodes disposed on the first and second regions, respectively, and first and second source/drain regions disposed on at least one side of the first and second gate electrodes, respectively. The device further includes first and second silicide regions in the first and second source/drain regions, respectively. A contact area between the first silicide region and the first source/drain region is differs in size from a contact area between the second silicide region and the second source/drain region. Methods of fabricating such devices are also provided.

Abstract translation: 半导体器件包括具有第一区域和第二区域的衬底，分别设置在第一和第二区域上的第一和第二栅极电极以及设置在第一和第二栅极的至少一侧上的第一和第二源极/漏极区域 电极。 该器件还分别包括第一和第二源极/漏极区域中的第一和第二硅化物区域。 第一硅化物区域和第一源极/漏极区域之间的接触区域的大小与第二硅化物区域和第二源极/漏极区域之间的接触面积不同。 还提供了制造这种装置的方法。

公开(公告)号：US10269928B2

公开(公告)日：2019-04-23

申请号：US15717843

申请日：2017-09-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Soo-Hun Hong ,  Hee-Soo Kang ,  Hyun-Jo Kim ,  Sang-Pil Sim ,  Hee-Don Jung

IPC: H01L29/161 ,  H01L29/66 ,  H01L27/088 ,  H01L29/06 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/08 ,  H01L29/16 ,  H01L21/762 ,  H01L29/78 ,  H01L29/165

Abstract: A semiconductor device includes a substrate including first to third fins aligned in a first direction, a first trench arranged between the first fin and the second fin, and a second trench arranged between the second fin and the third fin. The semiconductor device further includes a first field insulating film arranged in the first trench, a second field insulating film formed in the second trench, a first dummy gate arranged on the first field insulating film and a second dummy gate at least partly arranged on the second field insulating film. A lower surface of the second field insulating film is arranged to be lower than a lower surface of the first field insulating film.

公开(公告)号：US10205023B2

公开(公告)日：2019-02-12

申请号：US15694150

申请日：2017-09-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jae-Yup Chung ,  Hee-Soo Kang ,  Hee-Don Jeong ,  Se-Wan Park

IPC: H01L29/78 ,  H01L27/088

Abstract: A semiconductor device includes a first multi-channel active pattern, a field insulation layer disposed on the first multi-channel active pattern and including a first region and a second region, the first region having a top surface protruding from a top surface of the second region to a top surface of the first multi-channel active pattern, a first gate electrode crossing the first multi-channel active pattern, the first gate electrode being disposed on the field insulation layer, and a first source or drain disposed between the first gate electrode and the first region of the field insulation layer and including a first facet, the first facet being disposed adjacent to the first region of the field insulation layer at a point lower than the top surface of the first multi-channel active pattern.

公开(公告)号：US20170365716A1

公开(公告)日：2017-12-21

申请号：US15694150

申请日：2017-09-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae-Yup Chung ,  Hee-Soo Kang ,  Hee-Don Jeong ,  Se-Wan Park

IPC: H01L29/78 ,  H01L27/088

CPC classification number: H01L29/7848 ,  H01L27/0886 ,  H01L29/785

Abstract: A semiconductor device includes a first multi-channel active pattern, a field insulation layer disposed on the first multi-channel active pattern and including a first region and a second region, the first region having a top surface protruding from a top surface of the second region to a top surface of the first multi-channel active pattern, a first gate electrode crossing the first multi-channel active pattern, the first gate electrode being disposed on the field insulation layer, and a first source or drain disposed between the first gate electrode and the first region of the field insulation layer and including a first facet, the first facet being disposed adjacent to the first region of the field insulation layer at a point lower than the top surface of the first multi-channel active pattern.

公开(公告)号：US09012281B2

公开(公告)日：2015-04-21

申请号：US13829703

申请日：2013-03-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung-Dae Suk ,  Hee-Soo Kang ,  Sung-Il Park ,  Sang-Hoon Lee

IPC: H01L21/8238 ,  H01L27/092

CPC classification number: H01L27/0922 ,  H01L21/823871

Abstract: A semiconductor device includes a substrate having a first region and a second region, first and second gate electrodes disposed on the first and second regions, respectively, and first and second source/drain regions disposed on at least one side of the first and second gate electrodes, respectively. The device further includes first and second silicide regions in the first and second source/drain regions, respectively. A contact area between the first silicide region and the first source/drain region is differs in size from a contact area between the second silicide region and the second source/drain region. Methods of fabricating such devices are also provided.

Abstract translation: 半导体器件包括具有第一区域和第二区域的衬底，分别设置在第一和第二区域上的第一和第二栅极电极以及设置在第一和第二栅极的至少一侧上的第一和第二源极/漏极区域 电极。 该器件还分别包括第一和第二源极/漏极区域中的第一和第二硅化物区域。 第一硅化物区域和第一源极/漏极区域之间的接触区域的大小与第二硅化物区域和第二源极/漏极区域之间的接触面积不同。 还提供了制造这种装置的方法。

公开(公告)号：US08878309B1

公开(公告)日：2014-11-04

申请号：US14102897

申请日：2013-12-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Soo-Hun Hong ,  Hee-Soo Kang ,  Hyun-Jo Kim ,  Sang-Pil Sim ,  Hee-Don Jung

IPC: H01L29/78 ,  H01L27/088

CPC classification number: H01L27/0886 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823431 ,  H01L21/823481

Abstract: A semiconductor device includes a substrate having first, second and third fins longitudinally aligned in a first direction. A first trench extends between the first and second fins, and a second trench extends between the second and third fins. A first portion of field insulating material is disposed in the first trench, and a second portion of field insulating material is disposed in the second trench. An upper surface of the second portion of the field insulating material is recessed in the second trench at a level below uppermost surfaces of the second and third fins. A first dummy gate is disposed on an upper surface of the first portion of the field insulating material, and a second dummy gate at least partially extends into the second trench to the upper surface of the second portion of the field insulating material.

Abstract translation: 半导体器件包括具有沿第一方向纵向排列的第一，第二和第三鳍片的衬底。 第一沟槽在第一和第二鳍之间延伸，第二沟槽在第二和第三鳍之间延伸。 场绝缘材料的第一部分设置在第一沟槽中，场绝缘材料的第二部分设置在第二沟槽中。 场绝缘材料的第二部分的上表面在第二沟槽中凹陷在第二和第三鳍片的最上表面以下的水平面处。 第一伪栅极设置在场绝缘材料的第一部分的上表面上，并且第二伪栅极至少部分地延伸到第二沟槽中至场绝缘材料的第二部分的上表面。