公开(公告)号：US20230231049A1

公开(公告)日：2023-07-20

申请号：US17889744

申请日：2022-08-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dongsuk SHIN ,  Hyun-Kwan Yu ,  Sunyoung Lee ,  Ji Hoon Cha ,  Kyungyeon Hwang

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/423 ,  H01L29/51

CPC classification number: H01L29/783 ,  H01L29/0649 ,  H01L29/42364 ,  H01L29/512

Abstract: A semiconductor device includes a substrate including an active pattern, a channel pattern on the active pattern and including semiconductor patterns, a source/drain pattern connected to the semiconductor patterns, a gate electrode on the semiconductor patterns, and a gate dielectric layer between the gate electrode and the semiconductor patterns. An inner spacer of the gate dielectric layer includes a horizontal portion between the high-k dielectric layer and the second semiconductor pattern, a vertical portion between the high-k dielectric layer and the source/drain pattern, and a corner portion between the horizontal portion and the vertical portion. A first thickness of the horizontal portion is less than a second thickness of the vertical portion. The second thickness of the vertical portion is less than a third thickness of the corner portion.

公开(公告)号：US11069776B2

公开(公告)日：2021-07-20

申请号：US16789498

申请日：2020-02-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sanggil Lee ,  Namkyu Cho ,  Seokhoon Kim ,  Kang Hun Moon ,  Hyun-Kwan Yu ,  Sihyung Lee

IPC: H01L29/08 ,  H01L29/06 ,  H01L29/78 ,  H01L29/66 ,  H01L21/762

Abstract: Disclosed is a semiconductor device including a first active pattern that extends in a first direction on an active region of a substrate, a first source/drain pattern in a recess on an upper portion of the first active pattern, a gate electrode that runs across a first channel pattern on the upper portion of the first active pattern and extends in a second direction intersecting the first direction, and an active contact electrically connected to the first source/drain pattern.

公开(公告)号：US10896964B2

公开(公告)日：2021-01-19

申请号：US16252919

申请日：2019-01-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyun-Kwan Yu ,  Min-Hee Choi

IPC: H01L29/417 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/762

Abstract: A semiconductor device comprising a plurality of active patterns on a substrate. The semiconductor device may include a device isolation layer defining the plurality of active patterns, a gate electrode extending across the plurality of active patterns, and a source/drain pattern on the active patterns. The plurality of active patterns may comprise a first active pattern and a second active pattern. The source/drain pattern comprises a first part on the first active pattern, a second part on the second active pattern, and a third part extending from the first part and along an upper portion of the first active pattern. The device isolation layer comprises a first outer segment on a sidewall of the first active pattern below the source/drain pattern. A lowermost level of a bottom surface of the third part may be lower than an uppermost level of a top surface of the first outer segment.

公开(公告)号：US20180090589A1

公开(公告)日：2018-03-29

申请号：US15820171

申请日：2017-11-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyun-Kwan Yu ,  Kooktae Kim ,  Chanjin Park ,  Dongsuk Shin ,  Youngdal Lim ,  Sahwan Hong

IPC: H01L29/49 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/165 ,  H01L29/161 ,  H01L29/16 ,  H01L29/08 ,  H01L29/78

CPC classification number: H01L29/4991 ,  H01L21/7682 ,  H01L21/76897 ,  H01L21/823431 ,  H01L21/823481 ,  H01L23/485 ,  H01L27/0886 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/41791 ,  H01L29/66545 ,  H01L29/7848

Abstract: A semiconductor device includes a gate assembly disposed on a device isolation layer, a gate spacer disposed on a side surface of the gate assembly, a contact assembly disposed on the gate spacer, an air gap disposed between the device isolation layer and the contact assembly, and a first spacer capping layer disposed between the gate spacer and the air gap. The first spacer capping layer has an etch selectivity with respect to the gate spacer.