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公开(公告)号：US20230253449A1
公开(公告)日：2023-08-10
申请号：US17935528
申请日：2022-09-26
发明人： Dong Suk Shin , Hyun-Kwan Yu , Seok Hoon Kim , Pan Kwi Park , Yong Seung Kim , Jung Taek Kim
IPC分类号： H01L29/06 , H01L29/423 , H01L29/66 , H01L21/762
CPC分类号： H01L29/0653 , H01L21/76224 , H01L29/4232 , H01L29/66553
摘要： A semiconductor device includes a lower pattern extending in a first direction and sheet patterns spaced apart therefrom in a second direction, a gate structure on the lower pattern and including a gate insulating layer, a gate spacer, and a gate electrode, a source/drain pattern on the lower pattern and in contact with the sheet patterns and the gate insulating layer, and a first etch blocking pattern between the gate spacer and the source/drain pattern. The gate spacer includes an inner sidewall extending in the third direction, and a connection sidewall extending from the inner sidewall in the first direction. The source/drain pattern includes a semiconductor filling layer on a semiconductor liner layer that is in contact with the sheet pattern and includes a facet surface extending from the connection sidewall. The first etch blocking pattern is in contact with the facet surface and the connection sidewall.
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公开(公告)号：US11688781B2
公开(公告)日：2023-06-27
申请号：US17131977
申请日：2020-12-23
发明人： Hyun-Kwan Yu , Min-Hee Choi
IPC分类号： H01L29/417 , H01L27/088 , H01L21/8234 , H01L21/762
CPC分类号： H01L29/41791 , H01L21/76224 , H01L21/823425 , H01L21/823431 , H01L27/0886
摘要： A semiconductor device comprising a plurality of active patterns on a substrate. The semiconductor device may include a device isolation layer defining the plurality of active patterns, a gate electrode extending across the plurality of active patterns, and a source/drain pattern on the active patterns. The plurality of active patterns may comprise a first active pattern and a second active pattern. The source/drain pattern comprises a first part on the first active pattern, a second part on the second active pattern, and a third part extending from the first part and along an upper portion of the first active pattern. The device isolation layer comprises a first outer segment on a sidewall of the first active pattern below the source/drain pattern. A lowermost level of a bottom surface of the third part may be lower than an uppermost level of a top surface of the first outer segment.
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公开(公告)号：US11569350B2
公开(公告)日：2023-01-31
申请号：US17371858
申请日：2021-07-09
发明人： Sanggil Lee , Namkyu Cho , Seokhoon Kim , Kang Hun Moon , Hyun-Kwan Yu , Sihyung Lee
IPC分类号： H01L29/08 , H01L29/06 , H01L29/78 , H01L29/66 , H01L21/762
摘要： Disclosed is a semiconductor device including a first active pattern that extends in a first direction on an active region of a substrate, a first source/drain pattern in a recess on an upper portion of the first active pattern, a gate electrode that runs across a first channel pattern on the upper portion of the first active pattern and extends in a second direction intersecting the first direction, and an active contact electrically connected to the first source/drain pattern.
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公开(公告)号：US11010532B2
公开(公告)日：2021-05-18
申请号：US16794045
申请日：2020-02-18
发明人： Alexander Schmidt , Dong-Gwan Shin , Anthony Payet , Hyoung Soo Ko , Seok Hoon Kim , Hyun-Kwan Yu , Si Hyung Lee , In Kook Jang
IPC分类号： G06F30/367 , G06F30/398 , H01L27/02
摘要： A simulation method includes storing a plurality of structure parameters of transistors for a semiconductor chip, imaging generating a first local layout which includes a first structure parameter extracted from a semiconductor device included in the first local layout, the first structure parameter being an actual parameter determined using the imaging equipment, generating second to n-th local layouts by modifying the first structure parameter included in the first local layout, wherein the second to n-th local layouts respectively have second to n-th structure parameters modified from the first structure parameter, calculating first to n-th effective density factors (EDF) respectively for the first to n-th structure parameters, determining a first effective open silicon density for a first chip using the first to n-th effective density factors and a layout of the first chip, and calculating first to m-th epitaxy times for first to m-th effective open silicon densities.
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公开(公告)号：US11784255B2
公开(公告)日：2023-10-10
申请号：US17119507
申请日：2020-12-11
发明人： Hyun-Kwan Yu , Sung-Min Kim , Dong-Suk Shin , Seung-Hun Lee , Dong-Won Kim
IPC分类号： H01L29/06 , H01L29/78 , H01L29/66 , H01L27/088 , H01L21/8234 , H01L29/423 , H10B10/00 , H01L21/8238 , H01L21/84 , H01L27/12 , H01L27/092
CPC分类号： H01L29/785 , H01L21/823431 , H01L27/0886 , H01L29/0642 , H01L29/42372 , H01L29/66545 , H01L29/66795 , H10B10/12 , H01L21/823821 , H01L21/845 , H01L27/0924 , H01L27/1211
摘要： A semiconductor device may include a first active fin, a second active fin and a gate structure. The first active fin may extend in a first direction on a substrate and may include a first straight line extension portion, a second straight line extension portion, and a bent portion between the first and second straight line extension portions. The second active fin may extend in the first direction on the substrate. The gate structure may extend in a second direction perpendicular to the first direction on the substrate. The gate structure may cross one of the first and second straight line extension portions of the first active fin and may cross the second active fin.
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公开(公告)号：US09812557B2
公开(公告)日：2017-11-07
申请号：US15138234
申请日：2016-04-26
发明人： Hyun-Kwan Yu , Dong-Suk Shin , Woon-Ki Shin , Cheol-Woo Park , Ryong Ha , Han-Jin Lim
IPC分类号： H01L21/28 , H01L29/66 , H01L21/3213 , H01L21/02 , H01L29/78
CPC分类号： H01L29/66795 , H01L21/02068 , H01L21/32134 , H01L29/66545 , H01L29/7848
摘要： A method of manufacturing a semiconductor device includes forming an active fin extending longitudinally in a first direction along a surface of a substrate, forming a field insulating layer on the substrate, the field insulating layer covering a part of the active fin, forming a dummy gate electrode on the field insulating layer and the active fin, the dummy gate electrode extending in a second direction different from the first direction, forming a spacer on the sides of the dummy gate electrode, and removing the dummy gate electrode by a wet etching process that includes rinsing the dummy gate electrode intermittently during an etching away of the dummy gate electrode.
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公开(公告)号：US09812332B2
公开(公告)日：2017-11-07
申请号：US15398776
申请日：2017-01-05
发明人： Hyun-Kwan Yu , Woonki Shin , Moonhan Park , DongSuk Shin , HanJin Lim
IPC分类号： H01L21/461 , H01L21/306 , H01L21/02 , H01L21/8234
CPC分类号： H01L21/30604 , H01L21/02057 , H01L21/31111 , H01L21/31144 , H01L21/823418 , H01L21/823437 , H01L21/823468 , H01L21/823481
摘要： An etching method is disclosed. The etching method comprises providing on a substrate a structure comprising a recess region formed therein. The recess region includes an inner part and a mouth part whose width is less than that of the inner part. The etching method further comprises performing a clean-then-etch process to remove at least a portion of etching object formed outside the recess region. The performing a clean-then-etch process comprises performing a cleaning process to fill at least a portion of the recess region with a cleaning solution, and performing a wet etch process to the substrate in a state that the cleaning solution remains in the recess region.
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公开(公告)号：US11942528B2
公开(公告)日：2024-03-26
申请号：US18196533
申请日：2023-05-12
发明人： Hyun-Kwan Yu , Min-Hee Choi
IPC分类号： H01L29/417 , H01L21/762 , H01L21/8234 , H01L27/088
CPC分类号： H01L29/41791 , H01L21/76224 , H01L21/823425 , H01L21/823431 , H01L27/0886
摘要： A semiconductor device comprising a plurality of active patterns on a substrate. The semiconductor device may include a device isolation layer defining the plurality of active patterns, a gate electrode extending across the plurality of active patterns, and a source/drain pattern on the active patterns. The plurality of active patterns may comprise a first active pattern and a second active pattern. The source/drain pattern comprises a first part on the first active pattern, a second part on the second active pattern, and a third part extending from the first part and along an upper portion of the first active pattern. The device isolation layer comprises a first outer segment on a sidewall of the first active pattern below the source/drain pattern. A lowermost level of a bottom surface of the third part may be lower than an uppermost level of a top surface of the first outer segment.
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公开(公告)号：US09865698B2
公开(公告)日：2018-01-09
申请号：US15053842
申请日：2016-02-25
发明人： Hyun-Kwan Yu , Kooktae Kim , Chanjin Park , Dongsuk Shin , Youngdal Lim , Sahwan Hong
IPC分类号： H01L27/108 , H01L29/49 , H01L29/08 , H01L29/16 , H01L29/161 , H01L29/165 , H01L29/78 , H01L29/06 , H01L21/8234 , H01L27/088
CPC分类号： H01L29/4991 , H01L21/7682 , H01L21/76897 , H01L21/823431 , H01L21/823481 , H01L23/485 , H01L27/0886 , H01L29/0653 , H01L29/0847 , H01L29/1608 , H01L29/161 , H01L29/165 , H01L29/66545 , H01L29/7848
摘要： A semiconductor device includes a gate assembly disposed on a device isolation layer, a gate spacer disposed on a side surface of the gate assembly, a contact assembly disposed on the gate spacer, an air gap disposed between the device isolation layer and the contact assembly, and a first spacer capping layer disposed between the gate spacer and the air gap. The first spacer capping layer has an etch selectivity with respect to the gate spacer.
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10.发明申请公开(公告)号：US20140084379A1
公开(公告)日：2014-03-27
申请号：US14092016
申请日：2013-11-27
发明人： Yongkuk Jeong , Hyun-Kwan Yu , Kieun Kim
IPC分类号： H01L27/092
CPC分类号： H01L27/0922 , H01L21/3003 , H01L21/823807 , H01L21/823828 , H01L29/1054 , H01L29/66651 , H01L29/7843
摘要： A semiconductor device is fabricated by providing a substrate including a silicon channel layer and a silicon-germanium channel layer, forming gate structures disposed on the silicon channel layer and on the silicon-germanium channel layer, forming a first protection layer to cover the resultant structure including the gate structures, and injecting hydrogen and/or its isotopes into the silicon-germanium channel layer. The silicon and silicon-germanium channel layers may be oriented along a direction. Related devices are also described.
摘要翻译： 通过提供包括硅沟道层和硅 - 锗沟道层的衬底来制造半导体器件，形成设置在硅沟道层和硅 - 锗沟道层上的栅极结构，形成第一保护层以覆盖所得结构 包括栅极结构，以及将氢和/或其同位素注入到硅 - 锗通道层中。 硅和硅 - 锗沟道层可以沿<100>方向取向。 还描述了相关设备。
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