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    SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
    11.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 审中-公开
    半导体器件及其制造方法

    公开(公告)号：US20170069570A1

    公开(公告)日：2017-03-09

    申请号：US15229518

    申请日：2016-08-05

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jihoon Yoon ,  Shincheol Min ,  Hyun-Min Choi

    IPC: H01L23/525 ,  H01L21/66 ,  H01L27/112

    CPC classification number: H01L23/5256 ,  H01L22/14 ,  H01L27/11206 ,  H01L27/11582 ,  H01L28/00

    Abstract: In a semiconductor device and a method of manufacturing the same a fuse structure may be formed during formation of first to third contact plugs connected to a transistor. The fuse structure may include first and second fuse contact plugs having the same height as the first and second contact plugs, and a connection pattern having the same height as the third contact plug. The connection pattern may be connected between the first and second fuse contact plugs.

    Abstract translation: 在半导体器件及其制造方法中，可在形成连接到晶体管的第一至第三接触插塞的形成期间形成熔丝结构。 熔丝结构可以包括具有与第一和第二接触插塞相同的高度的第一和第二熔丝接触插塞，以及具有与第三接触插塞相同高度的连接图案。 连接图案可以连接在第一和第二熔丝接触插头之间。

    Semiconductor device and method for fabricating the same
    12.
    发明授权
    Semiconductor device and method for fabricating the same 有权
    半导体装置及其制造方法

    公开(公告)号：US09059090B2

    公开(公告)日：2015-06-16

    申请号：US14257466

    申请日：2014-04-21

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Ju-Youn Kim ,  Hyun-Min Choi ,  Sung-Kee Han ,  Je-Don Kim

    IPC: H01L21/28 ,  H01L21/285 ,  H01L29/66 ,  H01L21/8234

    CPC classification number: H01L21/28008 ,  H01L21/28518 ,  H01L21/823462 ,  H01L29/66545

    Abstract: A method of fabricating a semiconductor device includes forming a first gate pattern and a dummy gate pattern on a first active area and a second active area of a substrate, respectively, the first gate pattern including a first gate insulating layer and a silicon gate electrode, removing the dummy gate pattern to expose a surface of the substrate in the second active area, forming a second gate pattern including a second gate insulating layer and a metal gate electrode on the exposed surface of the substrate, the first gate insulating layer having a thickness larger than a thickness of the second gate insulating layer, and forming a gate silicide on the silicon gate electrode after forming the second gate pattern.

    Abstract translation: 一种制造半导体器件的方法包括分别在衬底的第一有源区和第二有源区上形成第一栅极图案和伪栅极图案，所述第一栅极图案包括第一栅极绝缘层和硅栅电极， 去除伪栅极图案以在第二有源区域中露出衬底的表面，在衬底的暴露表面上形成包括第二栅极绝缘层和金属栅电极的第二栅极图案，第一栅极绝缘层具有厚度 大于第二栅极绝缘层的厚度，以及在形成第二栅极图案之后在硅栅电极上形成栅极硅化物。

    E-fuse test device and semiconductor device including the same
    13.
    发明授权
    E-fuse test device and semiconductor device including the same 有权
    电子熔丝测试装置和包括其的半导体器件

    公开(公告)号：US09390812B2

    公开(公告)日：2016-07-12

    申请号：US14713458

    申请日：2015-05-15

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Hyun-Min Choi ,  In-Gyu Park ,  Jung-Hak Song

    IPC: G11C17/00 ,  G11C17/18 ,  G11C17/16 ,  G11C29/02 ,  G11C29/50 ,  G11C29/12

    CPC classification number: G11C17/18 ,  G11C17/16 ,  G11C29/027 ,  G11C2029/1206 ,  G11C2029/5006

    Abstract: An e-fuse test device is provided. The e-fuse test device may include a first transistor, and a fuse array connected to a source/drain terminal of the first transistor. The fuse array may include n fuse groups, each of the fuse groups may include one end, the other end, and m first fuse elements connected in series to each other between the one end and the other end, the one end of each of the fuse groups may be connected to each other, and the other end of each of the fuse groups may be connected to the source/drain terminal of the first transistor, and the n and m are natural numbers that are equal to or larger than two.

    Abstract translation: 提供电子熔断器测试装置。 电熔丝测试装置可以包括第一晶体管和连接到第一晶体管的源极/漏极端子的熔丝阵列。 熔丝阵列可以包括n个熔丝组，每个熔丝组可以包括在一端和另一端之间彼此串联连接的一端，另一端和m个第一熔丝元件， 熔丝组可以彼此连接，并且每个熔丝组的另一端可以连接到第一晶体管的源极/漏极端子，并且n和m是等于或大于2的自然数。

    Variable resistance memory device and a method of fabricating the same
    14.
    发明授权
    Variable resistance memory device and a method of fabricating the same 有权
    可变电阻存储器件及其制造方法

    公开(公告)号：US09293701B2

    公开(公告)日：2016-03-22

    申请号：US14527176

    申请日：2014-10-29

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Hyun-Min Choi ,  Juyoun Kim ,  Shigenobu Maeda ,  Jihoon Yoon ,  Sungman Lim

    IPC: H01L45/00 ,  H01L27/24

    CPC classification number: H01L45/1253 ,  H01L27/2436 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/146 ,  H01L45/147 ,  H01L45/148

    Abstract: A variable resistance memory device includes a gate pattern and a dummy gate pattern provided at the same level on a substrate, a first contact pattern provided on the dummy gate pattern, and a variable resistance pattern provided between the dummy gate pattern and the first contact pattern. The gate pattern and the dummy gate pattern define conductive electrodes of functional and non-functional transistors, respectively. The first contact pattern and the dummy gate pattern define upper and lower electrodes on the variable resistance pattern, respectively. Related fabrication methods are also discussed.

    Abstract translation: 可变电阻存储器件包括栅极图案和设置在基板上相同电平上的虚拟栅极图案，设置在伪栅极图案上的第一接触图案和设置在伪栅极图案和第一接触图案之间的可变电阻图案 。 栅极图案和虚拟栅极图案分别限定功能和非功能晶体管的导电电极。 第一接触图案和伪栅极图案分别限定可变电阻图案上的上电极和下电极。 还讨论了相关的制造方法。

    Variable Resistance Memory Device and a Method of Fabricating the Same
    15.
    发明申请
    Variable Resistance Memory Device and a Method of Fabricating the Same 有权
    可变电阻存储器件及其制造方法

    公开(公告)号：US20150144862A1

    公开(公告)日：2015-05-28

    申请号：US14527176

    申请日：2014-10-29

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Hyun-Min Choi ,  Juyoun Kim ,  Shigenobu Maeda ,  Jihoon Yoon ,  Sungman Lim

    IPC: H01L45/00 ,  H01L27/24

    CPC classification number: H01L45/1253 ,  H01L27/2436 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/146 ,  H01L45/147 ,  H01L45/148

    Abstract: A variable resistance memory device includes a gate pattern and a dummy gate pattern provided at the same level on a substrate, a first contact pattern provided on the dummy gate pattern, and a variable resistance pattern provided between the dummy gate pattern and the first contact pattern. The gate pattern and the dummy gate pattern define conductive electrodes of functional and non-functional transistors, respectively. The first contact pattern and the dummy gate pattern define upper and lower electrodes on the variable resistance pattern, respectively. Related fabrication methods are also discussed.

    Abstract translation: 可变电阻存储器件包括栅极图案和设置在基板上相同电平上的虚拟栅极图案，设置在伪栅极图案上的第一接触图案和设置在伪栅极图案和第一接触图案之间的可变电阻图案 。 栅极图案和虚拟栅极图案分别限定功能和非功能晶体管的导电电极。 第一接触图案和伪栅极图案分别限定可变电阻图案上的上电极和下电极。 还讨论了相关的制造方法。

    Anti-fuse one-time programmable (OTP) device
    16.
    发明授权
    Anti-fuse one-time programmable (OTP) device 有权

    公开(公告)号：US10685968B2

    公开(公告)日：2020-06-16

    申请号：US15399243

    申请日：2017-01-05

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jihoon Yoon ,  Hyun-Min Choi

    IPC: H01L27/112 ,  H01L23/525 ,  H01L23/522

    Abstract: A semiconductor device is disclosed. The semiconductor device including writing and reading gate electrodes respectively on first and second active regions on a substrate, a first gate insulation pattern between the first active region and the writing gate electrode, a second gate insulation pattern between the second active region and the reading gate electrode, first and second source/drain junction regions in the first and second active regions at sides of the writing and reading gate electrodes, and a connection structure that connects the first and second source/drain junction regions. The first active region has the same conductivity type as the source/drain junction regions. The second active region has a different conductivity type from the source/drain junction regions.

    Semiconductor device including fuse structure
    17.
    发明授权
    Semiconductor device including fuse structure 有权

    公开(公告)号：US10249566B2

    公开(公告)日：2019-04-02

    申请号：US15914142

    申请日：2018-03-07

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Hyun-Min Choi

    IPC: H01L23/525 ,  H01L23/528 ,  H01L23/522 ,  H01L23/532

    Abstract: An eFuse structure of a semiconductor device may include a first metal formed at a first level on a substrate, a second metal formed at a second level between the first level and the substrate, a third metal formed at a third level between the second level and the substrate, a first via connecting the first metal to the second metal, and a second via connecting the second metal to the third metal. The first metal may include a first portion extending in a first direction, a second portion extending in the first direction and being adjacent to the first portion, and a third portion connecting the first portion to the second portion. A first distance between the first portion and the second portion may be greater than a width of the second portion in a second direction perpendicular to the first direction.

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