公开(公告)号：US10522537B2

公开(公告)日：2019-12-31

申请号：US15937093

申请日：2018-03-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Changhwa Kim ,  Kyungin Choi ,  Hwichan Jun ,  Inchan Hwang

IPC: H01L27/08 ,  H01L27/088 ,  H01L21/768 ,  H01L21/02 ,  H01L21/8234 ,  H01L23/528 ,  H01L27/02 ,  H01L29/51 ,  H01L29/66 ,  H01L29/78 ,  H01L21/3115 ,  H01L21/311

Abstract: An integrated circuit device includes a substrate including a device active region, a fin-type active region protruding from the substrate on the device active region, a gate line crossing the fin-type active region and overlapping a surface and opposite sidewalls of the fin-type active region, an insulating spacer disposed on sidewalls of the gate line, a source region and a drain region disposed on the fin-type active region at opposite sides of the gate line, a first conductive plug connected the source or drain regions, and a capping layer disposed on the gate line and extending parallel to the gate line. The capping layer includes a first part overlapping the gate line, and a second part overlapping the insulating spacer. The first and second parts have different compositions with respect to each other. The second part contacts the first part and the first conductive plug.

公开(公告)号：US10115806B2

公开(公告)日：2018-10-30

申请号：US15165016

申请日：2016-05-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Chang-Hwa Kim ,  Joon-Gon Lee ,  Inchan Hwang

IPC: H01L21/70 ,  H01L29/66 ,  H01L29/78 ,  H01L21/768 ,  H01L23/485 ,  H01L23/532 ,  H01L23/522

Abstract: A semiconductor device includes a substrate with lower structures, an insulation layer covering the lower structures on the substrate, a contact hole through the insulation layer partially exposing the substrate, and a contact structure contacting the substrate through the contact hole, the contact structure including a barrier pattern having an upper barrier on an upper portion of a sidewall of the contact hole, and a lower barrier filling a lower portion of the contact hole, and a conductive contact pattern filling an upper portion of the contact hole defined by the upper barrier and the lower barrier.

公开(公告)号：US12131996B2

公开(公告)日：2024-10-29

申请号：US17739717

申请日：2022-05-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Saehan Park ,  Seungyoung Lee ,  Inchan Hwang

IPC: H01L23/528 ,  H01L21/78 ,  H01L21/822 ,  H01L21/8238 ,  H01L27/092

CPC classification number: H01L23/5286 ,  H01L21/7806 ,  H01L21/8221 ,  H01L21/823871 ,  H01L27/0922

Abstract: A semiconductor device including a wafer, a first semiconductor device and a second semiconductor device on a front side of the wafer, power rails on a back side of the wafer, a backside power distribution network (PDN) grid on the back side of the wafer, and front-side signal routing lines above the first and second semiconductor devices on the front side of the wafer. The second semiconductor device is stacked on the first semiconductor device, the backside PDN grid is coupled to the power rails, and the power rails are coupled to the first and second semiconductor devices.

公开(公告)号：US12087815B2

公开(公告)日：2024-09-10

申请号：US18187506

申请日：2023-03-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hwichan Jun ,  Inchan Hwang ,  Byounghak Hong

IPC: H01L29/06 ,  H01L27/088 ,  H01L29/40 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L29/0665 ,  H01L27/088 ,  H01L29/401 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66742 ,  H01L29/78696

Abstract: A semiconductor device includes a substrate; a 1st transistor formed above the substrate, and having a 1st transistor stack including a plurality of 1st channel structures, a 1st gate structure surrounding the 1st channel structures, and 1st and 2nd source/drain regions at both ends of the 1st transistor stack in a 1st channel length direction; and a 2nd transistor formed above the 1st transistor in a vertical direction, and having a 2nd transistor stack including a plurality of 2nd channel structures, a 2nd gate structure surrounding the 2nd channel structures, and 3rd and 4th source/drain regions at both ends of the 2nd transistor stack in a 2nd channel length direction, wherein the 3rd source/drain region does not vertically overlap the 1st source/drain region or the 2nd source/drain region, and the 4th source/drain region does not vertically overlap the 1st source/drain region or the 2nd source/drain region.

公开(公告)号：US12057448B2

公开(公告)日：2024-08-06

申请号：US18356545

申请日：2023-07-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Byounghak Hong ,  Seunghyun Song ,  Hwichan Jun ,  Inchan Hwang

IPC: H01L21/822 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/06 ,  H01L27/092 ,  H01L29/66

CPC classification number: H01L27/0688 ,  H01L21/8221 ,  H01L21/823437 ,  H01L21/823487 ,  H01L21/823828 ,  H01L21/823885 ,  H01L27/0922 ,  H01L29/66545

Abstract: A stacked semiconductor device includes: a substrate; a 1st transistor formed on a substrate, and including a 1st active region surrounded by a 1st gate structure and 1st source/drain regions; and a 2nd transistor stacked on the 1st transistor, and including a 2nd active region surrounded by a 2nd gate structure and 2nd source/drain regions, wherein the 1st active region and the 1st gate structure are vertically mirror-symmetric to the 2nd active region and the 2nd gate structure, respectively, with respect to a virtual plane therebetween.

公开(公告)号：US20240258328A1

公开(公告)日：2024-08-01

申请号：US18416473

申请日：2024-01-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Donghoon HWANG ,  Inchan Hwang ,  Hyojin Kim

IPC: H01L27/12

CPC classification number: H01L27/124 ,  H01L27/1266

Abstract: An integrated circuit device is provided. The device includes: lower source/drain areas; lower contacts respectively on bottom surfaces of the lower source/drain areas; upper source/drain areas spaced apart from the lower source/drain areas in a vertical direction; upper contacts respectively on upper surfaces of the upper source/drain areas; and a first vertical conductive rail electrically connected to a first contact of the lower contacts and the upper contacts, the first vertical conductive rail extending in the vertical direction, and including a first portion having a first upper surface at a first vertical level and a second portion having a second upper surface at a second vertical level lower than the first vertical level. The second portion overlaps a first upper contact among the upper contacts in the vertical direction.

公开(公告)号：US11735585B2

公开(公告)日：2023-08-22

申请号：US17223829

申请日：2021-04-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Byounghak Hong ,  Seunghyun Song ,  Hwichan Jun ,  Inchan Hwang

IPC: H01L27/06 ,  H01L21/8234 ,  H01L27/092 ,  H01L21/822 ,  H01L21/8238 ,  H01L29/66

CPC classification number: H01L27/0688 ,  H01L21/8221 ,  H01L21/823437 ,  H01L21/823487 ,  H01L21/823828 ,  H01L21/823885 ,  H01L27/0922 ,  H01L29/66545

Abstract: A stacked semiconductor device includes: a substrate; a 1st transistor formed on a substrate, and including a 1st active region surrounded by a 1st gate structure and 1st source/drain regions; and a 2nd transistor stacked on the 1st transistor, and including a 2nd active region surrounded by a 2nd gate structure and 2nd source/drain regions, wherein the 1st active region and the 1st gate structure are vertically mirror-symmetric to the 2nd active region and the 2nd gate structure, respectively, with respect to a virtual plane therebetween.

公开(公告)号：US11664433B2

公开(公告)日：2023-05-30

申请号：US17366534

申请日：2021-07-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byounghak Hong ,  Seunghyun Song ,  Inchan Hwang

IPC: H01L29/417 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/423 ,  H01L29/40 ,  H01L29/08 ,  H01L29/06

CPC classification number: H01L29/41775 ,  H01L21/823425 ,  H01L21/823475 ,  H01L27/088 ,  H01L29/0847 ,  H01L29/401 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/0665

Abstract: Integrated circuit devices may include a lower transistor and an upper transistor stacked on a substrate and may include a conductive contact. The upper transistor may include an upper source/drain region that overlaps a lower source/drain region of the lower transistor. The conductive contact may contact a side surface of the upper source/drain region and may overlap a center portion of the lower source/drain region. The side surface of the upper source/drain region may include a protrusion and a recess.

公开(公告)号：US11538814B2

公开(公告)日：2022-12-27

申请号：US17239060

申请日：2021-04-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Inchan Hwang ,  Hwichan Jun

IPC: H01L21/00 ,  H01L27/11 ,  H01L21/8238 ,  H01L23/528 ,  H01L27/092

Abstract: A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes a static random access memory (SRAM) including a plurality of transistors disposed in a first layer and a second layer. The first layer includes a first shared gate of a first transistor and a second shared gate of a second transistor, among the plurality of transistors. The second layer is disposed above the first layer and includes a third shared gate of a third transistor and a fourth shared gate of a fourth transistor, among the plurality of transistors. The third shared gate is disposed above the first shared gate, and the fourth shared gate is disposed above the second shared gate. The SRAM further includes a first shared contact, a second shared contact, a first cross-couple contact connecting the fourth shared gate and the first shared contact, and a second cross-couple contact connecting the third shared gate and the second shared contact.

公开(公告)号：US10043800B2

公开(公告)日：2018-08-07

申请号：US15442859

申请日：2017-02-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Changhwa Kim ,  Kyungin Choi ,  Hwichan Jun ,  Inchan Hwang

IPC: H01L21/8234 ,  H01L27/088 ,  H01L27/02 ,  H01L23/528 ,  H01L29/51 ,  H01L29/66

Abstract: An integrated circuit device includes a substrate including a device active region, a fin-type active region protruding from the substrate on the device active region, a gate line crossing the fin-type active region and overlapping a surface and opposite sidewalls of the fin-type active region, an insulating spacer disposed on sidewalls of the gate line, a source region and a drain region disposed on the fin-type active region at opposite sides of the gate line, a first conductive plug connected the source or drain regions, and a capping layer disposed on the gate line and extending parallel to the gate line. The capping layer includes a first part overlapping the gate line, and a second part overlapping the insulating spacer. The first and second parts have different compositions with respect to each other. The second part contacts the first part and the first conductive plug.