LIMITED LATERAL GROWTH OF S/D EPI BY OUTER DIELECTRIC LAYER IN 3-DIMENSIONAL STACKED DEVICE

    公开(公告)号:US20230335549A1

    公开(公告)日:2023-10-19

    申请号:US17866343

    申请日:2022-07-15

    摘要: An integrated circuit includes a first semiconductor device and a second semiconductor device adjacent to the first semiconductor device. Each of the first and second semiconductor devices includes a lower transistor and an upper transistor on the lower transistor, and the upper and lower transistors each include a source region, a drain region, and a channel region extending between the source region and the drain region. The integrated circuit also includes a first dielectric spacer extending along an inner sidewall of the channel region of the upper and/or lower transistor of the first semiconductor device, a second dielectric spacer facing the first dielectric spacer and extending along an inner sidewall of the channel region of the upper and/or lower transistor of the second semiconductor device. The integrated circuit also includes an interconnect contact between the first semiconductor device and the second semiconductor device.

    SELECTIVE DOUBLE DIFFUSION BREAK STRUCTURES FOR MULTI-STACK SEMICONDUCTOR DEVICE

    公开(公告)号:US20220336473A1

    公开(公告)日:2022-10-20

    申请号:US17382060

    申请日:2021-07-21

    摘要: A multi-stack semiconductor device includes: a plurality of lower transistor structures arranged on a lower stack and including a plurality of lower fin structures surrounded by a plurality of lower gate structures, respectively; a plurality of upper transistor structures arranged on an upper stack and including a plurality of upper fin structures surrounded by a plurality of upper gate structures, respectively; and at least one of a lower diffusion break structure on the lower stack and a upper diffusion break structure on the upper stack, wherein the lower diffusion break structure is formed between two adjacent lower gate structures, and isolates two lower transistor structures respectively including the two adjacent lower gate structures from each other, and the upper diffusion break structure is formed between two adjacent upper gate structures, and isolates two upper transistor structures respectively including the two adjacent upper gate structures from each other.