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公开(公告)号：US20230224265A1
公开(公告)日：2023-07-13
申请号：US18096757
申请日：2023-01-13
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Jieun KIM , Jinhong KIM , Chansung KIM , Yeseul PARK , Seokjae OH , Byoungho YUN , Seunghoon LEE , Yuseong JEON , Eunsang JEON
IPC: H04L51/046 , H04L51/216 , H04N21/4788 , H04N21/235 , H04N21/431
CPC classification number: H04L51/046 , H04L51/216 , H04N21/4788 , H04N21/235 , H04N21/4316
Abstract: Provided are a display apparatus and a method for providing a chat service for video content. A processor of the display apparatus receives video content. In response to requesting a chat room corresponding to the video content based on a user account, the processor receives chat messages and displays the received chat messages of the first chat room together with the video content on the display screen. In response to a chat room to which the user account belongs being changed from the first chat room to a second chat room based on an amount of chat messages of the user account transmitted to the chat server, the processor receives chat messages of the second chat room from the chat server, and displays the received chat messages of the second chat room through the display screen.
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12.发明申请公开(公告)号：US20230102906A1
公开(公告)日：2023-03-30
申请号：US17715473
申请日：2022-04-07
Applicant: Samsung Electronics Co., Ltd.
Inventor： Changsoo LEE , Jinhong KIM , Yongsung KIM , Jiwoon PARK , Jooho LEE , Yong-Hee CHO
IPC: H01L49/02 , H01L27/108
Abstract: A capacitor includes a lower electrode layer including a first conductive layer and a second conductive layer on the first conductive layer, the second conductive layer including SnO2 doped with an impurity; a dielectric layer on the second conductive layer, the dielectric layer including a rutile-phase oxide; and an upper electrode layer on the dielectric layer.
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公开(公告)号：US20210202833A1
公开(公告)日：2021-07-01
申请号：US16875119
申请日：2020-05-15
Applicant: Samsung Electronics Co., Ltd.
Inventor： Seyun KIM , Jinhong KIM , Soichiro MIZUSAKI , Jungho YOON , Youngjin CHO
Abstract: A variable resistance memory device includes a variable resistance layer, a first conductive element, and a second conductive element. The variable resistance layer includes a first layer including a first material and a second layer on the first layer and the second layer including a second material. The second material has a different valence than a valence of the first material. The first conductive element and the second conductive element are on the variable resistance layer and separated from each other to form an electric current path in the variable resistance layer in a direction perpendicular to a direction in which the first layer and the second layer are stacked.
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公开(公告)号：US20210153300A1
公开(公告)日：2021-05-20
申请号：US17137969
申请日：2020-12-30
Applicant: Samsung Electronics Co., Ltd.
Inventor： Jinhong KIM , Seyun KIM , Haengdeog KOH , Doyoon KIM , Hajin KIM , Soichiro MIZUSAKI , Minjong BAE , Changsoo LEE
Abstract: Provided are a structure, a planar heater including the same, a heating device including the planar heater, and a method of preparing the structure. The structure includes a metal substrate, an insulating layer disposed on the metal substrate, an electrode layer disposed on the insulating layer, and an electrically conductive layer disposed on the electrode layer, wherein a difference in a coefficient of thermal expansion (CTE) between the metal substrate and the insulating layer is 4 parts per million per degree Kelvin change in temperature (ppm/K) or less.
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15.发明申请公开(公告)号：US20190037644A1
公开(公告)日：2019-01-31
申请号：US16045834
申请日：2018-07-26
Applicant: Samsung Electronics Co., Ltd.
Inventor： Jinhong KIM , Seyun KIM , Haengdeog KOH , Doyoon KIM , Hajin KIM , Soichiro MIZUSAKI , Minjong BAE , Changsoo LEE
IPC: H05B1/02
Abstract: Provided are a structure, a planar heater including the same, a heating device including the planar heater, and a method of preparing the structure. The structure includes a metal substrate, an insulating layer disposed on the metal substrate, an electrode layer disposed on the insulating layer, and an electrically conductive layer disposed on the electrode layer, wherein a difference in a coefficient of thermal expansion (CTE) between the metal substrate and the insulating layer is 4 parts per million per degree Kelvin change in temperature (ppm/K) or less.
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Patent Agency Ranking
公开(公告)号：US20230225138A1
公开(公告)日：2023-07-13
申请号：US18185817
申请日：2023-03-17
Applicant: Samsung Electronics Co., Ltd.
Inventor： Yumin KIM , Seyun KIM , Jinhong KIM , Soichiro MIZUSAKI , Youngjin CHO
IPC: H01L47/00
CPC classification number: H10B63/84 , H10B63/34 , H10N70/011 , H10N70/8833 , H10N70/231 , H10N70/8828 , H10N70/841
Abstract: A memory device may include an insulating structure including a first surface and a protrusion portion protruding from the first surface in a first direction, a recording material layer on the insulating structure and extending along a protruding surface of the protrusion portion to cover the protrusion portion and extending onto the first surface of the insulating structure, a channel layer on the recording material layer and extending along a surface of the recording material layer, a gate insulating layer on the channel layer; and a gate electrode formed on the gate insulating layer at a location facing a second surface of the insulating structure. The second surface of the insulating structure may be a protruding upper surface of the protrusion portion.
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17.发明公开公开(公告)号：US20230143124A1
公开(公告)日：2023-05-11
申请号：US17861577
申请日：2022-07-11
Inventor： Changsoo LEE , Sangwoon LEE , Yongsung KIM , Jinhong KIM , Hyungjun KIM , Jooho LEE
IPC: H01L49/02 , H01L27/108 , H01G4/008
CPC classification number: H01L28/55 , H01L27/10852 , H01G4/008 , H01L28/75
Abstract: A capacitor includes a lower electrode including a perovskite material, an upper electrode spaced apart from the lower electrode, a dielectric layer positioned between the lower electrode and the upper electrode and including a perovskite material, and a passivation layer positioned between the lower electrode and the dielectric layer and including SrxTiyO3 in which a content of Ti is greater than a content of Sr.
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公开(公告)号：US20220302380A1
公开(公告)日：2022-09-22
申请号：US17395040
申请日：2021-08-05
Applicant: Samsung Electronics Co., Ltd.
Inventor： Soichiro MIZUSAKI , Doyoon KIM , Seyun KIM , Yumin KIM , Jinhong KIM , Youngjin CHO
Abstract: A variable resistance memory may include first and second conductive elements spaced apart from each other on a variable resistance layer. The variable resistance layer may include first to third oxide layers sequentially arranged in a direction perpendicular to a direction in which the first and second conductive elements are arranged. A dielectric constant of the second oxide layer may be greater than dielectric constants of the first and third oxide layers.
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公开(公告)号：US20220246679A1
公开(公告)日：2022-08-04
申请号：US17523381
申请日：2021-11-10
Applicant: Samsung Electronics Co., Ltd.
Inventor： Youngjin CHO , Seyun KIM , Yumin KIM , Doyoon KIM , Jinhong KIM , Soichiro MIZUSAKI
Abstract: A variable resistance memory device includes a support layer including an insulating material; a variable resistance layer on the support layer and including a variable resistance material; a capping layer between the support layer and the variable resistance layer and protecting the variable resistance layer; a channel layer on the variable resistance layer; a gate insulating layer on the channel layer; and a plurality of gate electrodes and a plurality of insulators alternately and repeatedly arranged on the gate insulating layer in a first direction parallel with the channel layer. The capping layer may maintain oxygen vacancies formed in the variable resistance layer.
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公开(公告)号：US20220020437A1
公开(公告)日：2022-01-20
申请号：US17306302
申请日：2021-05-03
Applicant: Samsung Electronics Co., Ltd.
Inventor： Yumin KIM , Seyun KIM , Jinhong KIM , Soichiro MIZUSAKI , Youngjin CHO
Abstract: A nonvolatile memory device and an operating method thereof are provided. The nonvolatile memory device includes a memory cell array including first to third memory cells sequentially arranged in a vertical stack structure and a control logic configured to apply a first non-selection voltage to the first memory cell, apply a second non-selection voltage different from the first non-selection voltage to the third memory cell, apply a selection voltage to the second memory cell, and select the second memory cell as a selection memory cell.
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