公开(公告)号：US11790146B2

公开(公告)日：2023-10-17

申请号：US17324829

申请日：2021-05-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaeha Lee ,  Jintae Kim ,  Seunghyun Yang ,  Dongyeon Heo

IPC: G06F30/392 ,  G06F30/398 ,  G06F30/394

CPC classification number: G06F30/392 ,  G06F30/394 ,  G06F30/398

Abstract: A semiconductor device including a standard cell is provided. The standard cell includes an active region; a gate structure intersecting the active region; a first conductive structure including: a first power supply line and a second power supply line; and a second conductive structure disposed on the first conductive structure, the second conductive structure including: first power distribution patterns spaced apart from each other a first boundary and electrically connected to the first power supply line, second power distribution patterns spaced apart from each other along a second boundary and electrically connected to the second power supply line, net metal lines disposed between and spaced apart from the first power distribution patterns and the second power distribution patterns, and electrically connected to a first portion of the signal lines, and pin metal lines electrically connected to a second portion of the signal lines.

公开(公告)号：US11387255B2

公开(公告)日：2022-07-12

申请号：US16989160

申请日：2020-08-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jintae Kim ,  Ha-Young Kim ,  Sinwoo Kim ,  Moo-Gyu Bae ,  Jaeha Lee

IPC: H01L27/11597 ,  H01L27/108 ,  H01L27/11524 ,  H01L27/06

Abstract: Disclosed is a semiconductor device comprising a logic cell that is on a substrate and includes first and second active regions spaced apart from each other in a first direction, first and second active patterns that are respectively on the first and second active regions and extend in a second direction intersecting the first direction, gate electrodes extending in the first direction and running across the first and second active patterns, first connection lines that are in a first interlayer dielectric layer on the gate electrodes and extend parallel to each other in the second direction, and second connection lines that are in a second interlayer dielectric layer on the first interlayer dielectric layer and extend parallel to each other in the first direction.

公开(公告)号：US20220092249A1

公开(公告)日：2022-03-24

申请号：US17324829

申请日：2021-05-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaeha LEE ,  Jintae Kim ,  Seunghyun Yang ,  Dongyeon Heo

IPC: G06F30/392 ,  G06F30/394 ,  G06F30/398

Abstract: A semiconductor device including a standard cell is provided. The standard cell includes an active region; a gate structure intersecting the active region; a first conductive structure including: a first power supply line and a second power supply line; and a second conductive structure disposed on the first conductive structure, the second conductive structure including: first power distribution patterns spaced apart from each other a first boundary and electrically connected to the first power supply line, second power distribution patterns spaced apart from each other along a second boundary and electrically connected to the second power supply line, net metal lines disposed between and spaced apart from the first power distribution patterns and the second power distribution patterns, and electrically connected to a first portion of the signal lines, and pin metal lines electrically connected to a second portion of the signal lines.

公开(公告)号：US20180367144A1

公开(公告)日：2018-12-20

申请号：US16056072

申请日：2018-08-06

Applicant: Samsung Electronics Co., Ltd

Inventor： Dalhee Lee ,  Jintae Kim ,  Jaeha Lee

IPC: H03K19/0185

Abstract: A level shifting circuit includes a level shifting portion configured to receive an input signal and generate an output signal, and a current adjustment circuit connected between the level shifting portion and a drive high voltage node at which a drive high voltage is applied. The current adjustment circuit is configured to adjust an amount of current provided from the drive high voltage node to the level shifting portion.

公开(公告)号：US09536946B2

公开(公告)日：2017-01-03

申请号：US14833983

申请日：2015-08-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jae-Ho Park ,  Taejoong Song ,  Sanghoon Baek ,  Jintae Kim ,  Giyoung Yang ,  Hyosig Won

IPC: H01L27/088 ,  H01L29/06 ,  H01L29/08 ,  H01L29/417 ,  H01L27/02 ,  H01L27/092 ,  H01L21/8238

CPC classification number: H01L29/0642 ,  H01L21/768 ,  H01L21/76816 ,  H01L21/823871 ,  H01L27/0207 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/0847 ,  H01L29/41758 ,  H01L29/41791

Abstract: A semiconductor device includes a substrate having an active region, a gate structure intersecting the active region and extending in a first direction parallel to a top surface of the substrate, a first source/drain region and a second source/drain region disposed in the active region at both sides of the gate structure, respectively, and a first modified contact and a second modified contact in contact with the first source/drain region and the second source/drain region, respectively. The distance between the gate structure and the first modified contact is smaller than the distance between the gate structure and the second modified contact.

Abstract translation: 半导体器件包括具有有源区的衬底，与有源区相交且在平行于衬底顶表面的第一方向上延伸的栅极结构，设置在有源区中的第一源极/漏极区和第二源极/漏极区 分别与第一源极/漏极区域和第二源极/漏极区域接触的第一修改触点和第二修改触点。 栅极结构和第一改性接触之间的距离小于栅极结构和第二改性接触之间的距离。

公开(公告)号：US20250063782A1

公开(公告)日：2025-02-20

申请号：US18592999

申请日：2024-03-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Panjae Park ,  Jintae Kim ,  Kang-ill Seo

IPC: H01L29/417 ,  H01L27/06 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

Abstract: An integrated circuit device includes a wimpy transistor stack on a substrate, wherein the wimpy transistor stack comprises: an upper transistor comprising: a plurality of upper channel regions stacked in a vertical direction; and an upper source/drain region that contacts at least one of the plurality of upper channel regions; a lower transistor that is between the substrate and the upper transistor and comprises: a plurality of lower channel regions stacked in the vertical direction; and a lower source/drain region that contacts at least one of the plurality of lower channel regions; and a source/drain isolation layer separating the upper source/drain region from the lower source/drain region, wherein the source/drain isolation layer contacts a lowermost one of the plurality of upper channel regions and/or an uppermost one of the plurality of lower channel regions.

公开(公告)号：US12081230B2

公开(公告)日：2024-09-03

申请号：US17871538

申请日：2022-07-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyoungwon Lee ,  Jintae Kim ,  Sungwon Roh

IPC: H03M1/12 ,  H03M1/36

CPC classification number: H03M1/365

Abstract: An analog-to-digital converter (ADC) for converting an analog signal into a digital signal includes an amplifier circuit configured to receive the analog signal, and to generate a plurality of amplifier signals by amplifying the analog signal; a comparison circuit configured to compare a plurality of voltage levels corresponding to the plurality of amplifier signals with a positive reference voltage level and a negative reference voltage level, and to output conversion target signals based on a result of the comparison; and a converter circuit configured to convert the conversion target signals into a plurality of digital signals.

公开(公告)号：US10749527B2

公开(公告)日：2020-08-18

申请号：US16056072

申请日：2018-08-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dalhee Lee ,  Jintae Kim ,  Jaeha Lee

IPC: H03K19/0175 ,  H03K19/0185

Abstract: A level shifting circuit includes a level shifting portion configured to receive an input signal and generate an output signal, and a current adjustment circuit connected between the level shifting portion and a drive high voltage node at which a drive high voltage is applied. The current adjustment circuit is configured to adjust an amount of current provided from the drive high voltage node to the level shifting portion.