中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

24 records (took 0.029 seconds)

    Integrated circuit including clubfoot structure conductive patterns
    12.
    发明授权
    Integrated circuit including clubfoot structure conductive patterns 有权

    公开(公告)号：US10790305B2

    公开(公告)日：2020-09-29

    申请号：US16409129

    申请日：2019-05-10

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jung-ho Do ,  Ji-Su Yu ,  Hyeon-gyu You ,  Seung-Young Lee ,  Jae-Boong Lee ,  Jong-Hoon Jung

    IPC: H01L23/52 ,  H01L27/118 ,  H01L27/02

    Abstract: An integrated circuit includes a standard cell. The standard cell may include a plurality of gate lines and a plurality of first wirings. The plurality of first wirings may include a clubfoot structure conductive pattern that includes a first conductive pattern and a second conductive pattern spaced apart from each other. Each of the first conductive pattern and the second conductive pattern may include a first line pattern extending in a first direction and a second line pattern protruding from one end of the first line pattern in a direction perpendicular to the first direction. The plurality of gate lines may be spaced apart from each other by a first pitch in the first direction, and the plurality of second wirings may be spaced apart from each other by a second pitch in the first direction. The first pitch may be greater than the second pitch.

    Integrated circuits including standard cells and method of manufacturing the integrated circuits
    13.
    发明授权
    Integrated circuits including standard cells and method of manufacturing the integrated circuits 有权

    公开(公告)号：US10790273B2

    公开(公告)日：2020-09-29

    申请号：US16203845

    申请日：2018-11-29

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jung-ho Do

    IPC: H01L27/02 ,  H01L27/118 ,  G06F30/392 ,  G06F30/394

    Abstract: Provided are integrated circuits including a plurality of standard cells aligned along a plurality of rows. The integrated circuit includes first standard cells aligned on the first row and including first conductive patterns to which a first supply voltage is applied in a conductive layer and second standard cells aligned on the second row which is adjacent to the first row in the conductive layer and including second conductive patterns to which the first supply voltage is applied in the conductive layer. A pitch between the first conductive patterns and the second conductive patterns may be less than a pitch provided by single-patterning.

    Logic cell including deep via contact and wiring layers located at different levels
    19.
    发明授权
    Logic cell including deep via contact and wiring layers located at different levels 有权

    公开(公告)号：US10707163B2

    公开(公告)日：2020-07-07

    申请号：US16200747

    申请日：2018-11-27

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Vincent Chun Fai Lau ,  Jung-ho Do ,  Byung-sung Kim ,  Chul-hong Park

    IPC: H01L23/522 ,  H01L27/088 ,  H01L27/02 ,  H01L27/118 ,  H01L23/528

    Abstract: A semiconductor device includes a substrate; a plurality of conductive areas formed on the substrate at a first vertical level; a first wiring layer formed on the substrate at a second vertical level which is higher than the first vertical level, the first wiring layer including first lines that extend in a first direction, one first line of the first lines connected to a first conductive area selected from the plurality of conductive areas through a via contact; a second wiring layer formed on the substrate at a third vertical level which is higher than the second vertical level, the second wiring layer including second lines that extend in a second direction that crosses the first direction, one second line of the second lines connected to a second conductive area selected from the plurality of conductive areas; and a deep via contact spaced apart from lines of the first wiring layer in a horizontal direction and extending from the second conductive area to the one second line.

Patent Agency Ranking