公开(公告)号：US11348807B2

公开(公告)日：2022-05-31

申请号：US16925982

申请日：2020-07-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junghoon Kang

IPC: H01L21/48 ,  H01L23/538 ,  H01L25/18 ,  H01L25/00 ,  H01L21/683 ,  H01L23/498

Abstract: A semiconductor package includes an interposer having a separation layer on a rear surface of which a plurality of first recesses is arranged. A plurality of wiring structures is stacked on the separation layer alternately with a plurality of insulation interlayers. A plurality of semiconductor devices is arranged, side by side, on the interposer side and connected to a plurality of the wiring structures. A plurality of contact terminals on the rear surface of the separation layer is connected to the plurality of the wiring structures through the separation layer. A flatness deterioration of the interposer is minimized and the contact surface between the interposer and under fill resin is enlarged.

公开(公告)号：US20210210360A1

公开(公告)日：2021-07-08

申请号：US16925982

申请日：2020-07-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junghoon Kang

IPC: H01L21/48 ,  H01L23/538 ,  H01L21/683 ,  H01L25/18 ,  H01L25/00

Abstract: A semiconductor package includes an interposer having a separation layer on a rear surface of which a plurality of first recesses is arranged. A plurality of wiring structures is stacked on the separation layer alternately with a plurality of insulation interlayers. A plurality of semiconductor devices is arranged, side by side, on the interposer side and connected to a plurality of the wiring structures. A plurality of contact terminals on the rear surface of the separation layer is connected to the plurality of the wiring structures through the separation layer. A flatness deterioration of the interposer is minimized and the contact surface between the interposer and under fill resin is enlarged.

公开(公告)号：US20250093594A1

公开(公告)日：2025-03-20

申请号：US18747906

申请日：2024-06-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junghoon Kang ,  Daegon Kim

IPC: G02B6/42 ,  H01L23/00 ,  H01L23/13 ,  H01L23/48 ,  H01L23/498 ,  H01L23/538 ,  H01L25/16 ,  H01L27/144

Abstract: A semiconductor package includes a package substrate including an alignment hole extending inwardly from a side surface of the package substrate, a photonic integrated circuit chip disposed on the package substrate, the of the package substrate chip including a groove extending inwardly from a side surface of the PIC chip and a photo-electron conversion unit including an edge coupler, and an optical fiber connector including a frame, an optical fiber mounted in the groove of the of the package substrate chip and passing through the frame, and an alignment pin extending from the frame to an inside of the alignment hole, wherein the edge coupler is located at one end of the photo-electron conversion unit.

公开(公告)号：US12100668B2

公开(公告)日：2024-09-24

申请号：US18496372

申请日：2023-10-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junghoon Kang

IPC: H01L23/31 ,  H01L23/00 ,  H01L23/538 ,  H01L23/544 ,  H01L25/065

CPC classification number: H01L23/544 ,  H01L23/3121 ,  H01L23/5384 ,  H01L23/5386 ,  H01L24/16 ,  H01L25/0657 ,  H01L2224/16225 ,  H01L2225/06517

Abstract: A semiconductor package includes a first semiconductor chip; an encapsulant covering at least a portion of the first semiconductor chip; insulating layers provided on the encapsulant, each of the insulating layers being transparent or translucent; and wiring layers provided on the encapsulant, the wiring layers being partially covered by the insulating layers, wherein an outermost insulating layer of the insulating layers comprises a first region and a second region, a color of the first region is different from a color of the second region, the second region surrounds the first region, and at least one marking pattern comprising at least one step portion is provided in the first region of the outermost insulating layer.

公开(公告)号：US20240213174A1

公开(公告)日：2024-06-27

申请号：US18515797

申请日：2023-11-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junghoon Kang ,  Unbyoung Kang ,  Jinsu Kim ,  Seungwan Shin ,  Byoungwook Jang

IPC: H01L23/544 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L25/065 ,  H01L25/10

CPC classification number: H01L23/544 ,  H01L23/3128 ,  H01L23/49811 ,  H01L24/16 ,  H01L24/20 ,  H01L25/0657 ,  H01L25/105 ,  H01L2223/54433 ,  H01L2224/16225 ,  H01L2224/21 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06562

Abstract: A semiconductor package includes a lower redistribution wiring layer having a first region and a second region adjacent the first region and including first redistribution wirings; a semiconductor chip on the first region of the lower redistribution wiring layer and electrically connected to the first redistribution wirings; a sealing member on a side surface of the semiconductor chip and on the lower redistribution wiring layer; a plurality of vertical conductive structures penetrating the sealing member on the second region of the lower redistribution wiring layer and electrically connected to the first redistribution wirings; a marking pattern on the semiconductor chip; seed layer pads on respective end portions of the vertical conductive structures that are exposed by the sealing member at an upper surface thereof; and an upper redistribution wiring layer on the sealing member and the marking pattern and including second redistribution wirings.

公开(公告)号：US11837553B2

公开(公告)日：2023-12-05

申请号：US17405696

申请日：2021-08-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junghoon Kang

IPC: H01L23/538 ,  H01L23/544 ,  H01L23/31 ,  H01L25/065 ,  H01L23/00

CPC classification number: H01L23/544 ,  H01L23/3121 ,  H01L23/5384 ,  H01L23/5386 ,  H01L24/16 ,  H01L25/0657 ,  H01L2224/16225 ,  H01L2225/06517

Abstract: A semiconductor package includes a first semiconductor chip; an encapsulant covering at least a portion of the first semiconductor chip; insulating layers provided on the encapsulant, each of the insulating layers being transparent or translucent; and wiring layers provided on the encapsulant, the wiring layers being partially covered by the insulating layers, wherein an outermost insulating layer of the insulating layers comprises a first region and a second region, a color of the first region is different from a color of the second region, the second region surrounds the first region, and at least one marking pattern comprising at least one step portion is provided in the first region of the outermost insulating layer.

公开(公告)号：US20220165634A1

公开(公告)日：2022-05-26

申请号：US17405696

申请日：2021-08-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junghoon Kang

IPC: H01L23/31 ,  H01L23/538 ,  H01L23/00 ,  H01L25/065

Abstract: A semiconductor package includes a first semiconductor chip; an encapsulant covering at least a portion of the first semiconductor chip; insulating layers provided on the encapsulant, each of the insulating layers being transparent or translucent; and wiring layers provided on the encapsulant, the wiring layers being partially covered by the insulating layers, wherein an outermost insulating layer of the insulating layers comprises a first region and a second region, a color of the first region is different from a color of the second region, the second region surrounds the first region, and at least one marking pattern comprising at least one step portion is provided in the first region of the outermost insulating layer.