公开(公告)号：US20200243521A1

公开(公告)日：2020-07-30

申请号：US16848902

申请日：2020-04-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Taewon HA ,  Juyoun KIM ,  Sang Min LEE ,  Moon-Sun HONG ,  Seki HONG

IPC: H01L27/088 ,  H01L21/8234 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/66 ,  H01L29/78 ,  H01L29/417 ,  H01L29/51 ,  H01L21/28

Abstract: A semiconductor device includes a substrate having an active region, and first to third transistors on the active region of the substrate, each of the first to third transistors including a dielectric layer on the substrate, a metal layer on the dielectric layer, a barrier layer between the dielectric layer and the metal layer, and a work function layer between the dielectric layer and the barrier layer, wherein the barrier layer of the third transistor is in contact with the dielectric layer of the third transistor, and wherein a threshold voltage of the second transistor is greater than a threshold voltage of the first transistor and less than a threshold voltage of the third transistor.

公开(公告)号：US20190304972A1

公开(公告)日：2019-10-03

申请号：US16260275

申请日：2019-01-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Juyoun KIM ,  Jin-Wook KIM

IPC: H01L27/088 ,  H01L29/66 ,  H01L29/78 ,  H01L29/49 ,  H01L21/28 ,  H01L21/8234

Abstract: A semiconductor device includes a substrate, an interlayer dielectric layer on the substrate and having a first opening and a second opening, a first gate pattern in the first opening and including a first work function pattern, a first conductive blocking pattern, a first blocking pattern, and a conductive pattern that are stacked, and a second gate pattern in the second opening. The second gate pattern includes a second work function pattern of a material the same as a material of the first work function pattern, and a second conductive blocking pattern on the second work function pattern and filling the second opening. The second conductive blocking pattern includes a material that is different from a material of the conductive pattern and is different from a material of the first blocking pattern.

公开(公告)号：US20230178625A1

公开(公告)日：2023-06-08

申请号：US17892415

申请日：2022-08-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Juyoun KIM ,  Sangjung KANG ,  Jinwoo KIM ,  Yoori SUNG

IPC: H01L29/49 ,  H01L29/51 ,  H01L29/08 ,  H01L29/423 ,  H01L21/28 ,  H01L21/8234

CPC classification number: H01L29/4966 ,  H01L29/517 ,  H01L29/0847 ,  H01L29/42316 ,  H01L21/28026 ,  H01L21/823456

Abstract: A semiconductor device includes a substrate including PMOSFET and NMOSFET regions; and first/second transistors on the PMOSFET/NMOSFET regions, respectively, wherein the first transistor includes a first gate dielectric layer on the substrate; a first lower metal pattern on the first gate dielectric layer; a second lower metal pattern on the first lower metal pattern; and a first intermediate pattern between the first and second lower metal patterns, the second transistor includes a second gate dielectric layer on the substrate; a third lower metal pattern on the second gate dielectric layer; and a second intermediate pattern between the second gate dielectric layer and the third lower metal pattern, the first and second intermediate patterns each include lanthanum, the first to third lower metal patterns each include a metal nitride, and a thickness of the first lower metal pattern is greater than a thickness of the third lower metal pattern.

公开(公告)号：US20210408232A1

公开(公告)日：2021-12-30

申请号：US17106971

申请日：2020-11-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Juyoun KIM

IPC: H01L29/06 ,  H01L27/11

Abstract: An integrated circuit device includes an active area extending in a first direction on a substrate and a gate line extending in a second direction intersecting with the first direction to intersect with the active area. The gate line comprises a first sidewall and a second sidewall opposite to each other. The first sidewall has a convex shape. The second sidewall has a concave shape.

公开(公告)号：US20210398978A1

公开(公告)日：2021-12-23

申请号：US17101472

申请日：2020-11-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Juyoun KIM ,  Seulgi YUN ,  Seki HONG

IPC: H01L27/092 ,  H01L21/8238

Abstract: A semiconductor device includes first and second transistors on a substrate. The first transistor includes a first N-type active region, a first gate electrode having a first work function layer, and a first gate dielectric layer having high-k dielectrics containing La. The first work function layer includes a first layer having TiON, a second layer having TiN or TiON, a third layer having TiON, a fourth layer having TiN, and a fifth layer having TiAlC. The second transistor includes a first P-type active region, a second gate electrode having a second work function layer, and a second gate dielectric layer having high-k dielectrics. The second work function layer includes the fifth layer directly contacting the second gate dielectric layer.

公开(公告)号：US20170200652A1

公开(公告)日：2017-07-13

申请号：US15468631

申请日：2017-03-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Juyoun KIM

IPC: H01L21/8238 ,  H01L29/51 ,  H01L27/092 ,  H01L29/49 ,  H01L21/28

CPC classification number: H01L21/823821 ,  H01L21/28088 ,  H01L21/823814 ,  H01L21/823842 ,  H01L21/845 ,  H01L27/088 ,  H01L27/092 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545

Abstract: In a semiconductor device, a first active area, a second active area, and a third active area are formed on a substrate. A first gate electrode is formed on the first active area, a second gate electrode is formed on the second active area, and a third gate electrode is formed on the third active area. The first gate electrode has a first P-work-function metal layer, a first capping layer, a first N-work-function metal layer, a first barrier metal layer, and a first conductive layer. The second gate electrode has a second capping layer, a second N-work-function metal layer, a second barrier metal layer, and a second conductive layer. The third gate electrode has a second P-work-function metal layer, a third capping layer, a third N-work-function metal layer, and a third barrier metal layer. The third gate electrode does not have the first and second conductive layers.